Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9197
-gerrit
commit df621d3b76761797ab2e14eed618123a0c84cf6c Author: Kane Chen kane.chen@intel.com Date: Tue Sep 9 15:53:09 2014 -0700
broadwell: pcie update from BWG/RC code
According to BIOS spec 8.14 B0:D28:F0[5:4] should be set to 11
BRANCH=none BUG=chrome-os-partner:28234 TEST=build ok, boot to Auron and Samus make sure register is set and PCIE is working
Change-Id: I4a7e990993c230dfc1ba83ea75f56757c2c18e46 Signed-off-by: Stefan Reinauer reinauer@chromium.org Original-Commit-Id: 82826e3c44c26252697677ec08b95a8f174bc360 Original-Change-Id: I7c37245053ceae460dac0f18363f585244db72f8 Original-Signed-off-by: Kane Chen kane.chen@intel.com Original-Reviewed-on: https://chromium-review.googlesource.com/217414 Original-Reviewed-by: Duncan Laurie dlaurie@chromium.org --- src/soc/intel/broadwell/pcie.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index bd1c55a..f63f6d5 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -113,6 +113,7 @@ static void root_port_init_config(device_t dev) rpc.pin_ownership = pci_read_config32(dev, 0x410); root_port_config_update_gbe_port();
+ pcie_update_cfg8(dev, 0xe2, ~(3 << 4), (3 << 4)); if (dev->chip_info != NULL) { config_t *config = dev->chip_info; rpc.coalesce = config->pcie_port_coalesce;