Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6463
-gerrit
commit 8512e12c9f8b236e9e1e2b4a99a8cfde14aaa61f Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Sat Aug 2 20:08:35 2014 +1000
superio/smsc/sio1036: Fix hardcoded TTY0 base addr and .c include
Compile romstage component as link-time symbols. Pass CONFIG_TTY0_BASE as argument instead of hard coding and playing funny business with the pre-processor. Fix board to match.
Change-Id: If6d0d5389bd4e7765bb6056cf488c94fd45915c2 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/mainboard/amd/dinar/Kconfig | 1 + src/mainboard/amd/dinar/devicetree.cb | 2 +- src/mainboard/amd/dinar/romstage.c | 10 +++------ src/superio/smsc/sio1036/Makefile.inc | 1 + src/superio/smsc/sio1036/sio1036.h | 5 +++++ src/superio/smsc/sio1036/sio1036_early_init.c | 31 +++++++++++++-------------- 6 files changed, 26 insertions(+), 24 deletions(-)
diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig index e826459..b71c5a5 100644 --- a/src/mainboard/amd/dinar/Kconfig +++ b/src/mainboard/amd/dinar/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AGESA_FAMILY15 select NORTHBRIDGE_AMD_CIMX_RD890 select SOUTHBRIDGE_AMD_CIMX_SB700 + select SUPERIO_SMSC_SIO1036 select SUPERIO_SMSC_SCH4037 select BOARD_ROMSIZE_KB_2048 select HAVE_OPTION_TABLE diff --git a/src/mainboard/amd/dinar/devicetree.cb b/src/mainboard/amd/dinar/devicetree.cb index 09becd4..7a59fd2 100644 --- a/src/mainboard/amd/dinar/devicetree.cb +++ b/src/mainboard/amd/dinar/devicetree.cb @@ -85,7 +85,7 @@ chip northbridge/amd/agesa/family15/root_complex irq 0x70 = 1 # PS/2 keyboard interrupt irq 0x72 = 12 # PS/2 mouse interrupt end - end #SIO SMSC307 + end #SIO SMSC SCH4037 end #LPC device pci 14.4 on end # PCI bridge, 0x4384 device pci 14.5 on end # USB 3 diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 842b4f0..8cc3d9a 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -33,12 +33,12 @@ #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "superio/smsc/sch4037/sch4037_early_init.c" -#include "superio/smsc/sio1036/sio1036_early_init.c" +#include <superio/smsc/sio1036/sio1036.h> #include "cpu/x86/lapic.h" #include "nb_cimx.h" #include <sb_cimx.h>
-#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) +#define SERIAL_DEV PNP_DEV(0x4e, SIO1036_SP1)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -50,11 +50,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sch4037_early_init(0x2e);
- /* Detect SMSC SIO1036 LPC Debug Card status */ - if (detect_sio1036_chip(0x4E)) { - /* Found SMSC SIO1036 LPC Debug Card */ - sio1036_early_init(0x4E); - } + sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
post_code(0x31); console_init(); diff --git a/src/superio/smsc/sio1036/Makefile.inc b/src/superio/smsc/sio1036/Makefile.inc index f09d451..c4b6138 100644 --- a/src/superio/smsc/sio1036/Makefile.inc +++ b/src/superio/smsc/sio1036/Makefile.inc @@ -17,4 +17,5 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA #
+romstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += sio1036_early_init.c ramstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += superio.c diff --git a/src/superio/smsc/sio1036/sio1036.h b/src/superio/smsc/sio1036/sio1036.h index e61b600..fa52a1a 100644 --- a/src/superio/smsc/sio1036/sio1036.h +++ b/src/superio/smsc/sio1036/sio1036.h @@ -26,4 +26,9 @@ #define LPT_POWER_DOWN (1 << 2) #define IR_OUPUT_MUX (1 << 6)
+#include <arch/io.h> +#include <stdint.h> + +void sio1036_enable_serial(device_t dev, u16 iobase); + #endif /* SUPERIO_SMSC_1306_H */ diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c index 52232a5..5f10230 100644 --- a/src/superio/smsc/sio1036/sio1036_early_init.c +++ b/src/superio/smsc/sio1036/sio1036_early_init.c @@ -20,50 +20,49 @@ /* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */
#include <arch/io.h> +#include <stdint.h> + #include "sio1036.h"
-#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3F8 -#endif static inline void sio1036_enter_conf_state(device_t dev) { - unsigned port = dev>>8; + unsigned port = dev >> 8; outb(0x55, port); }
static inline void sio1036_exit_conf_state(device_t dev) { - unsigned port = dev>>8; + unsigned port = dev >> 8; outb(0xaa, port); }
+/* Detect SMSC SIO1036 LPC Debug Card status */ static u8 detect_sio1036_chip(unsigned port) { - device_t dev; - dev = PNP_DEV (port, SIO1036_SP1); + device_t dev = PNP_DEV(port, SIO1036_SP1); unsigned data; + sio1036_enter_conf_state (dev); data = pnp_read_config (dev, 0x0D); sio1036_exit_conf_state(dev); - /* detect smsc sio1036 chip */ + + /* Detect SMSC SIO1036 chip */ if (data == 0x82) { /* Found SMSC SIO1036 chip */ return 0; } else { - return -1; + return 1; }; }
-static inline void sio1036_early_init(unsigned port) +void sio1036_enable_serial(device_t dev, u16 iobase) { - device_t dev; - dev = PNP_DEV (port, SIO1036_SP1); + unsigned port = dev >> 8;
- if (detect_sio1036_chip(port) != 0) { - /* Not found SMSC SIO1036 */ + if (detect_sio1036_chip(port) != 0) return; - } + sio1036_enter_conf_state (dev);
/* Enable SMSC UART 0 */ @@ -91,7 +90,7 @@ static inline void sio1036_early_init(unsigned port)
/* Enable SMSC UART 0 */ /*Set base io address */ - pnp_write_config (dev, 0x25, (u8)((u16)CONFIG_TTYS0_BASE >> 2)); + pnp_write_config (dev, 0x25, (u8)(iobase >> 2));
/* Set UART IRQ onto 0x04 */ pnp_write_config (dev, 0x28, 0x04);