Subrata Banik has uploaded a new change for review. ( https://review.coreboot.org/19676 )
Change subject: soc/intel/skylake: Option to enable/disable EIST ......................................................................
soc/intel/skylake: Option to enable/disable EIST
Set MSR 0x1A0 bit[16] based on EIST config option. Default HWP enabled on SKL hence disable EIST and ACPI P-state table.
Change-Id: I2b7374a8a04b596edcc88165b64980b7aa09e2a7 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/cpu.c 4 files changed, 19 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/19676/1
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index e8d0c16..64438bd 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -523,9 +523,10 @@ generate_c_state_entries(is_s0ix_enable, max_c_state);
- /* Generate P-state tables */ - generate_p_state_entries(core_id, - cores_per_package); + if (config->eist_enable) + /* Generate P-state tables */ + generate_p_state_entries(core_id, + cores_per_package);
acpigen_pop_len(); } diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index b474ca2..43c921e 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -459,6 +459,12 @@
/* Enable SGX feature */ u8 sgx_enable; + + /* Enable/Disable EIST + * 1b - Enabled + * 0b - Disabled + */ + u8 eist_enable; };
typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 2d9b864..8a7cb21 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -261,6 +261,9 @@ /* Enable PMC XRAM read */ tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable;
+ /* Enable/Disable EIST */ + tconfig->Eist = config->eist_enable; + soc_irq_settings(params); }
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 38fe54c..588ffab 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -245,12 +245,17 @@
static void configure_misc(void) { + device_t dev = SA_DEV_ROOT; + config_t *conf = dev->chip_info; msr_t msr;
msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + if (conf->eist_enable) + msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + else + msr.lo &= ~(1 << 16); /* Enhanced SpeedStep Disable */ wrmsr(IA32_MISC_ENABLE, msr);
/* Disable Thermal interrupts */