[coreboot-gerrit] Change in coreboot[master]: mb/intel/dg43gt: Add romstage timestamp

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/21635

Change subject: mb/intel/dg43gt: Add romstage timestamp
......................................................................

mb/intel/dg43gt: Add romstage timestamp

Change-Id: I0383dd9b582d5c77be66ecd74bcf1a438f874cc7
Signed-off-by: Arthur Heymans 
---
M src/mainboard/intel/dg43gt/romstage.c
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/21635/1

diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c
index 5b98163..6944b18 100644
--- a/src/mainboard/intel/dg43gt/romstage.c
+++ b/src/mainboard/intel/dg43gt/romstage.c
@@ -25,6 +25,7 @@
 #include <superio/winbond/common/winbond.h>
 #include <lib.h>
 #include <northbridge/intel/x4x/iomap.h>
+#include <timestamp.h>

#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
 #define LPC_DEV PCI_DEV(0, 0x1f, 0)
@@ -71,6 +72,9 @@
    u8 boot_path = 0;
    u8 s3_resume;

+	timestamp_init(get_initial_timestamp());
+	timestamp_add_now(TS_START_ROMSTAGE);
+
    /* Disable watchdog timer */
    RCBA32(0x3410) = RCBA32(0x3410) | 0x20;

@@ -93,7 +97,9 @@
    	boot_path = BOOT_PATH_WARM_RESET;

printk(BIOS_DEBUG, "Initializing memory\n");
+	timestamp_add_now(TS_BEFORE_INITRAM);
    sdram_initialize(boot_path, spd_addrmap);
+	timestamp_add_now(TS_AFTER_INITRAM);
    quick_ram_check();
    printk(BIOS_DEBUG, "Memory initialized\n");