[coreboot-gerrit] [S] Change in coreboot[master]: soc/intel/xeon_sp: Cache DRAM with TSEG for FSP-S execution time

[Arthur Heymans (Code Review)]

Attention is currently required from: Arthur Heymans, Patrick Rudolph, Johnny Lin, Paul Menzel, Christian Walter, Shuming Chu (Shuming).

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71085 )

Change subject: soc/intel/xeon_sp: Cache DRAM with TSEG for FSP-S execution time
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Patch Set 4:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/71085/comment/693bb016_b7b376fc 
PS4, Line 7: soc/intel/xeon_sp: Improve FSP-S boottime for xeon-sp platform
> Maybe: […]

Done

https://review.coreboot.org/c/coreboot/+/71085/comment/4a8fb5fa_515119e8 
PS4, Line 12:
> Maybe paste the MTRR before and after for easy comparison?

The patch was made 18 months ago iirc. Sorry I don't have those available anymore. I think TSEG top was pretty well aligned so not so many MTRR were needed but I can't confirm this.