[coreboot-gerrit] [M] Change in coreboot[main]: arch/riscv: Factor out common romstage code

[Maximilian Brune (Code Review)]

Attention is currently required from: Arthur Heymans, Felix Held, Philipp Hug, Ron Minnich.

Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/83098?usp=email )

Change subject: arch/riscv: Factor out common romstage code
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Patch Set 5:

(1 comment)

File src/mainboard/sifive/hifive-unmatched/romstage.c:

https://review.coreboot.org/c/coreboot/+/83098/comment/3e7d5253_30313be6?usp... :
PS5, Line 19: 	console_init();
> console_init is already called in the common code before calling this function. […]

UART subsystem depends on `clock_init()`. I meant to remove it and do it like on the unleashed board. I have a few more patches and tests to do on the unmatched board anyway. If you don't mind I will take care of that in another patch.
Acknowledged