Sathya Prakash M R has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31280
Change subject: mb/google/hatch: Enable Audio support ......................................................................
mb/google/hatch: Enable Audio support
Following changes are done to enable Audio support on hatch 1. Enable I2C4 device at 400Khz at 3.3V 2. Configure GPIO for HP INT and SPEAKER EN 3. Add ACPI entry for RT5682 4. Enable DMIC, I2S0 and I2S1 lines.
BUG=b:123738217 BRANCH=none TEST=check SSDT table for RT5682 entry. verify audio over SOF.
Change-Id: I93f3917c19cc3f0f8fd7b5e1b4d9b24a59f45f84 Signed-off-by: Sathya Prakash M R sathya.prakash.m.r@intel.com --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/gpio.c 2 files changed, 46 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/31280/1
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index eb528f2..6d0ea04 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -27,6 +27,7 @@ #| | before memory is up | #| I2C0 | Touchpad | #| I2C1 | Touch screen | + #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ .gspi[0] = { @@ -39,6 +40,9 @@ .i2c[1] = { .speed = I2C_SPEED_FAST, }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, }"
# FSP configuration @@ -92,6 +96,12 @@ register "PcieClkSrcUsage[3]" = "13" register "PcieClkSrcClkReq[3]" = "3"
+ #Enable I2S Audio, SSP0, SSP1 and DMIC0 + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkSsp0" = "1" + register "PchHdaAudioLinkSsp1" = "1" + register "PchHdaAudioLinkDmic0" = "1" + device cpu_cluster 0 on device lapic 0 on end end @@ -223,7 +233,21 @@ device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on end # SATA - device pci 19.0 on end # I2C #4 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H0_IRQ)" + register "probed" = "1" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 off end # UART #2 device pci 1a.0 off end # eMMC @@ -264,7 +288,13 @@ end # eSPI Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 off end # Intel HDA + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index f8d5d7d..5820af7 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -65,6 +65,10 @@ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* PCH_I2C_TOUCHSCREEN_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* PCH_I2C_AUDIO_SDA */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* PCH_I2C_AUDIO_SCL */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* PCH_WP_OD */ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* H1_PCH_INT_ODL */ @@ -143,6 +147,16 @@ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* SD_WP => NC */ PAD_NC(GPP_G7, DN_20K), + /*AUDIO IRQ*/ + PAD_CFG_GPI_APIC(GPP_H0, NONE, PLTRST, LEVEL, INVERT), + /*SPEAKER SD MODE ENABLE*/ + PAD_CFG_GPO(GPP_H3, 0, DEEP), + /* DMIC_CLK_0_SNDW4_CLK */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* DMIC_DATA_0_SNDW4_DATA */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + /* SPP_MCLK */ + PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
/* PCH_I2C_PEN_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),