Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46878 )
Change subject: soc/mediatek/mt8192: add clkbuf and srclken_rc MT6359P driver ......................................................................
Patch Set 41:
(3 comments)
https://review.coreboot.org/c/coreboot/+/46878/41/src/soc/mediatek/mt8192/in... File src/soc/mediatek/mt8192/include/soc/pmif.h:
https://review.coreboot.org/c/coreboot/+/46878/41/src/soc/mediatek/mt8192/in... PS41, Line 176: #define PMIFSPI_INF_EN_SRCLKEN_RC_HW_MSK 0x1 : #define PMIFSPI_INF_EN_SRCLKEN_RC_HW_SHFT 4 DEFINE_BIT
https://review.coreboot.org/c/coreboot/+/46878/41/src/soc/mediatek/mt8192/in... PS41, Line 188: #define PMIFSPI_SPM_SLEEP_REQ_SEL_MSK 0x3 : #define PMIFSPI_SPM_SLEEP_REQ_SEL_SHFT 0 DEFINE_BITFIELD
https://review.coreboot.org/c/coreboot/+/46878/41/src/soc/mediatek/mt8192/pm... File src/soc/mediatek/mt8192/pmif.c:
https://review.coreboot.org/c/coreboot/+/46878/41/src/soc/mediatek/mt8192/pm... PS41, Line 183: unsigned int spi_sleep_ctrl, spmi_sleep_ctrl; : unsigned int spi_mode_ctrl, spmi_mode_ctrl; : unsigned int inf_en, other_inf_en, arb_en; : : spi_sleep_ctrl = read32(&pmif_spi_arb[0].mtk_pmif->sleep_protection_ctrl); : spmi_sleep_ctrl = read32(&pmif_spmi_arb[0].mtk_pmif->sleep_protection_ctrl); : spi_mode_ctrl = read32(&pmif_spi_arb[0].mtk_pmif->spi_mode_ctrl); : spmi_mode_ctrl = read32(&pmif_spmi_arb[0].mtk_pmif->spi_mode_ctrl); : inf_en = read32(&pmif_spi_arb[0].mtk_pmif->inf_en); : other_inf_en = read32(&pmif_spi_arb[0].mtk_pmif->other_inf_en); : arb_en = read32(&pmif_spi_arb[0].mtk_pmif->arb_en); : : if (mode == PMIF_VLD_RDY) { : /* spm and scp sleep request disable spi and spmi */ : spi_sleep_ctrl = (spi_sleep_ctrl : & ~(PMIFSPI_SPM_SLEEP_REQ_SEL_MSK << PMIFSPI_SPM_SLEEP_REQ_SEL_SHFT)) : | (0x1 << PMIFSPI_SPM_SLEEP_REQ_SEL_SHFT); : spi_sleep_ctrl = (spi_sleep_ctrl : & ~(PMIFSPI_SCP_SLEEP_REQ_SEL_MSK << PMIFSPI_SCP_SLEEP_REQ_SEL_SHFT)) : | (0x1 << PMIFSPI_SCP_SLEEP_REQ_SEL_SHFT); : : spmi_sleep_ctrl = (spmi_sleep_ctrl : & ~(PMIFSPMI_SPM_SLEEP_REQ_SEL_MSK << PMIFSPMI_SPM_SLEEP_REQ_SEL_SHFT)) : | (0x1 << PMIFSPMI_SPM_SLEEP_REQ_SEL_SHFT); : spmi_sleep_ctrl = (spmi_sleep_ctrl : & ~(PMIFSPMI_SCP_SLEEP_REQ_SEL_MSK << PMIFSPMI_SCP_SLEEP_REQ_SEL_SHFT)) : | (0x1 << PMIFSPMI_SCP_SLEEP_REQ_SEL_SHFT); : : /* pmic vld/rdy control spi mode enable*/ : spi_mode_ctrl = (spi_mode_ctrl : & ~(PMIFSPI_MD_CTL_PMIF_RDY_MSK << PMIFSPI_MD_CTL_PMIF_RDY_SHFT)) : | (0x1 << PMIFSPI_MD_CTL_PMIF_RDY_SHFT); : /* srclken control spi mode disable*/ : spi_mode_ctrl = (spi_mode_ctrl : & ~(PMIFSPI_MD_CTL_SRCLK_EN_MSK << PMIFSPI_MD_CTL_SRCLK_EN_SHFT)) : | (0x0 << PMIFSPI_MD_CTL_SRCLK_EN_SHFT); : /* vreq control spi mode disable*/ : spi_mode_ctrl = (spi_mode_ctrl : & ~(PMIFSPI_MD_CTL_SRVOL_EN_MSK << PMIFSPI_MD_CTL_SRVOL_EN_SHFT)) : | (0x0 << PMIFSPI_MD_CTL_SRVOL_EN_SHFT); : spmi_mode_ctrl = (spmi_mode_ctrl : & ~(PMIFSPMI_MD_CTL_PMIF_RDY_MSK << PMIFSPMI_MD_CTL_PMIF_RDY_SHFT)) : | (0x1 << PMIFSPMI_MD_CTL_PMIF_RDY_SHFT); : spmi_mode_ctrl = (spmi_mode_ctrl : & ~(PMIFSPMI_MD_CTL_SRCLK_EN_MSK << PMIFSPMI_MD_CTL_SRCLK_EN_SHFT)) : | (0x0 << PMIFSPMI_MD_CTL_SRCLK_EN_SHFT); : spmi_mode_ctrl = (spmi_mode_ctrl : & ~(PMIFSPMI_MD_CTL_SRVOL_EN_MSK << PMIFSPMI_MD_CTL_SRVOL_EN_SHFT)) : | (0x0 << PMIFSPMI_MD_CTL_SRVOL_EN_SHFT); : : /* srclken rc interface enable*/ : inf_en = (inf_en & ~(PMIFSPI_INF_EN_SRCLKEN_RC_HW_MSK : << PMIFSPI_INF_EN_SRCLKEN_RC_HW_SHFT)) : | (0x1 << PMIFSPI_INF_EN_SRCLKEN_RC_HW_SHFT); : : /* dcxo interface disable */ : other_inf_en = (other_inf_en : & ~(PMIFSPI_OTHER_INF_DXCO0_EN_MSK << PMIFSPI_OTHER_INF_DXCO0_EN_SHFT)) : | (0x0 << PMIFSPI_OTHER_INF_DXCO0_EN_SHFT); : other_inf_en = (other_inf_en : & ~(PMIFSPI_OTHER_INF_DXCO1_EN_MSK << PMIFSPI_OTHER_INF_DXCO1_EN_SHFT)) : | (0x0 << PMIFSPI_OTHER_INF_DXCO1_EN_SHFT); : /*srclken enable, dcxo0,1 disable*/ : arb_en = (arb_en & ~(PMIFSPI_ARB_EN_SRCLKEN_RC_HW_MSK : << PMIFSPI_ARB_EN_SRCLKEN_RC_HW_SHFT)) : | (0x1 << PMIFSPI_ARB_EN_SRCLKEN_RC_HW_SHFT); : arb_en = (arb_en & ~(PMIFSPI_ARB_EN_DCXO_CONN_MSK : << PMIFSPI_ARB_EN_DCXO_CONN_SHFT)) : | (0x0 << PMIFSPI_ARB_EN_DCXO_CONN_SHFT); : arb_en = (arb_en & ~(PMIFSPI_ARB_EN_DCXO_NFC_MSK : << PMIFSPI_ARB_EN_DCXO_NFC_SHFT)) : | (0x0 << PMIFSPI_ARB_EN_DCXO_NFC_SHFT); : } else if (mode == PMIF_SLP_REQ) { : /* spm and scp sleep request enable spi and spmi */ : spi_sleep_ctrl = (spi_sleep_ctrl : & ~(PMIFSPI_SPM_SLEEP_REQ_SEL_MSK << PMIFSPI_SPM_SLEEP_REQ_SEL_SHFT)) : | (0x0 << PMIFSPI_SPM_SLEEP_REQ_SEL_SHFT); : spi_sleep_ctrl = (spi_sleep_ctrl : & ~(PMIFSPI_SCP_SLEEP_REQ_SEL_MSK << PMIFSPI_SCP_SLEEP_REQ_SEL_SHFT)) : | (0x0 << PMIFSPI_SCP_SLEEP_REQ_SEL_SHFT); : : spmi_sleep_ctrl = (spmi_sleep_ctrl : & ~(PMIFSPMI_SPM_SLEEP_REQ_SEL_MSK << PMIFSPMI_SPM_SLEEP_REQ_SEL_SHFT)) : | (0x0 << PMIFSPMI_SPM_SLEEP_REQ_SEL_SHFT); : spmi_sleep_ctrl = (spmi_sleep_ctrl : & ~(PMIFSPMI_SCP_SLEEP_REQ_SEL_MSK << PMIFSPMI_SCP_SLEEP_REQ_SEL_SHFT)) : | (0x0 << PMIFSPMI_SCP_SLEEP_REQ_SEL_SHFT); : : /* pmic vld/rdy control spi mode disable*/ : spi_mode_ctrl = (spi_mode_ctrl : & ~(PMIFSPI_MD_CTL_PMIF_RDY_MSK << PMIFSPI_MD_CTL_PMIF_RDY_SHFT)) : | (0x0 << PMIFSPI_MD_CTL_PMIF_RDY_SHFT); : /* srclken control spi mode enable*/ : spi_mode_ctrl = (spi_mode_ctrl : & ~(PMIFSPI_MD_CTL_SRCLK_EN_MSK << PMIFSPI_MD_CTL_SRCLK_EN_SHFT)) : | (0x1 << PMIFSPI_MD_CTL_SRCLK_EN_SHFT); : /* vreq control spi mode enable*/ : spi_mode_ctrl = (spi_mode_ctrl : & ~(PMIFSPI_MD_CTL_SRVOL_EN_MSK << PMIFSPI_MD_CTL_SRVOL_EN_SHFT)) : | (0x1 << PMIFSPI_MD_CTL_SRVOL_EN_SHFT); : : spmi_mode_ctrl = (spmi_mode_ctrl : & ~(PMIFSPMI_MD_CTL_PMIF_RDY_MSK << PMIFSPMI_MD_CTL_PMIF_RDY_SHFT)) : | (0x0 << PMIFSPMI_MD_CTL_PMIF_RDY_SHFT); : spmi_mode_ctrl = (spmi_mode_ctrl : & ~(PMIFSPMI_MD_CTL_SRCLK_EN_MSK << PMIFSPMI_MD_CTL_SRCLK_EN_SHFT)) : | (0x1 << PMIFSPMI_MD_CTL_SRCLK_EN_SHFT); : spmi_mode_ctrl = (spmi_mode_ctrl : & ~(PMIFSPMI_MD_CTL_SRVOL_EN_MSK << PMIFSPMI_MD_CTL_SRVOL_EN_SHFT)) : | (0x1 << PMIFSPMI_MD_CTL_SRVOL_EN_SHFT); : : /* srclken rc interface disable*/ : inf_en = (inf_en & ~(PMIFSPI_INF_EN_SRCLKEN_RC_HW_MSK : << PMIFSPI_INF_EN_SRCLKEN_RC_HW_SHFT)) : | (0x0 << PMIFSPI_INF_EN_SRCLKEN_RC_HW_SHFT); : /* dcxo interface enable */ : other_inf_en = (other_inf_en : & ~(PMIFSPI_OTHER_INF_DXCO0_EN_MSK << PMIFSPI_OTHER_INF_DXCO0_EN_SHFT)) : | (0x1 << PMIFSPI_OTHER_INF_DXCO0_EN_SHFT); : other_inf_en = (other_inf_en : & ~(PMIFSPI_OTHER_INF_DXCO1_EN_MSK << PMIFSPI_OTHER_INF_DXCO1_EN_SHFT)) : | (0x1 << PMIFSPI_OTHER_INF_DXCO1_EN_SHFT); : : /*srclken disable, dcxo0,1 enable*/ : arb_en = (arb_en & ~(PMIFSPI_ARB_EN_SRCLKEN_RC_HW_MSK : << PMIFSPI_ARB_EN_SRCLKEN_RC_HW_SHFT)) : | (0x0 << PMIFSPI_ARB_EN_SRCLKEN_RC_HW_SHFT); : arb_en = (arb_en & ~(PMIFSPI_ARB_EN_DCXO_CONN_MSK : << PMIFSPI_ARB_EN_DCXO_CONN_SHFT)) : | (0x1 << PMIFSPI_ARB_EN_DCXO_CONN_SHFT); : arb_en = (arb_en & ~(PMIFSPI_ARB_EN_DCXO_NFC_MSK : << PMIFSPI_ARB_EN_DCXO_NFC_SHFT)) : | (0x1 << PMIFSPI_ARB_EN_DCXO_NFC_SHFT); : : } else : return; : : write32(&pmif_spi_arb[0].mtk_pmif->sleep_protection_ctrl, spi_sleep_ctrl); : write32(&pmif_spmi_arb[0].mtk_pmif->sleep_protection_ctrl, spmi_sleep_ctrl); : write32(&pmif_spi_arb[0].mtk_pmif->spi_mode_ctrl, spi_mode_ctrl); : write32(&pmif_spmi_arb[0].mtk_pmif->spi_mode_ctrl, spmi_mode_ctrl); : write32(&pmif_spi_arb[0].mtk_pmif->inf_en, inf_en); : write32(&pmif_spi_arb[0].mtk_pmif->other_inf_en, other_inf_en); : write32(&pmif_spi_arb[0].mtk_pmif->arb_en, arb_en); : } use DEFINE_BITFIELD, DEFINE_BIT and SET32_BITFIELDS
if (mode == PMIF_VLD_RDY) { spi_spm_sleep_req = 0x1; scp_spm_sleep_req = 0x1; ... } else if (mode == PMIF_SLP_REQ) { spi_spm_sleep_req = 0x0; scp_spm_sleep_req = 0x0; ... } else { return; }
SET32_BITFIELDS(&pmif_spi_arb[0].mtk_pmif->sleep_protection_ctrl, PMIFSPI_SPM_SLEEP_REQ_SEL, spi_spm_sleep_req, PMIFSPI_SCP_SLEEP_REQ_SEL, scp_spm_sleep_req); SET32_BITFIELDS(....);