[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Save/restore BAR registers when extract cpu cras...

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Kane Chen, Patrick Rudolph.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59355 )

Change subject: soc/intel/alderlake: Save/restore BAR registers when extract cpu crashlog
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Patch Set 6:

(1 comment)

Patchset:

PS6:
> Hi Tim,  […]

It's just a PCI device like any other that has BARs that can be assigned by coreboot's resource allocator during PCI enumeration, just like i2c, spi, lpc, pcie controllers, etc. The resource allocator will read the BARs for their size requirements and carve out space for each. All the board has to do is turn the `crashlog` device on in the devicetree and it will get a valid BAR during enumeration.