Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59886 )
Change subject: soc/intel/tigerlake: Hook up DPTF device to devicetree ......................................................................
soc/intel/tigerlake: Hook up DPTF device to devicetree
Hook up `Device4Enable` FSP setting to devicetree state and drop its redundant devicetree setting `Device4Enable`.
The following mainboards enable the DPTF device in the devicetree despite `Device4Enable` is not being set.
* google/deltaur
Thus, set it to off to keep the current state unchanged.
Change-Id: Ic7636fc4f63d4beab92e742a6882ac55af2565bc Signed-off-by: Felix Singer felixsinger@posteo.net Reviewed-on: https://review.coreboot.org/c/coreboot/+/59886 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb M src/mainboard/system76/darp7/devicetree.cb M src/mainboard/system76/galp5/devicetree.cb M src/mainboard/system76/gaze16/devicetree.cb M src/mainboard/system76/lemp10/devicetree.cb M src/mainboard/system76/oryp8/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 12 files changed, 8 insertions(+), 30 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 643bdc1..aeab2d4 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -130,7 +130,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Graphics - device pci 04.0 on end # DPTF + device pci 04.0 off end # DPTF device pci 05.0 off end # IPU device pci 06.0 off end # PEG60 device pci 07.0 on end # TBT_PCIe0 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index ca9661f..1958e99 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -295,8 +295,6 @@ .tdp_pl4 = 83, }"
- register "Device4Enable" = "1" - register "tcc_offset" = "10" # TCC of 90
register "CnviBtCore" = "true" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 0e34eb2..47c4368 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -119,9 +119,6 @@ # Enable DPTF register "dptf_enable" = "1"
- # Enable Processor Thermal Control - register "Device4Enable" = "1" - # Add PL1 and PL2 values register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ .tdp_pl1_override = 15, diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 17af01a..cd5493b 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -123,9 +123,6 @@ # Enable DPTF register "dptf_enable" = "1"
- # Enable Processor Thermal Control - register "Device4Enable" = "1" - # Add PL1 and PL2 values register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ .tdp_pl1_override = 9, diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb index 5c55dce..a3fc715 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb @@ -76,9 +76,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on # SA Thermal Device - register "Device4Enable" = "1" - end + device pci 04.0 on end # SA Thermal Device device pci 05.0 off end # IPU device pci 06.0 off end # PEG60 device pci 07.0 on end # TBT_PCIe0 diff --git a/src/mainboard/system76/darp7/devicetree.cb b/src/mainboard/system76/darp7/devicetree.cb index 7a3e072..dc369ad 100644 --- a/src/mainboard/system76/darp7/devicetree.cb +++ b/src/mainboard/system76/darp7/devicetree.cb @@ -105,9 +105,7 @@
register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device ref dptf on - register "Device4Enable" = "1" - end + device ref dptf on end device ref peg on # PCIe PEG0 x4, Clock 0 (SSD1) register "PcieClkSrcUsage[0]" = "0x40" diff --git a/src/mainboard/system76/galp5/devicetree.cb b/src/mainboard/system76/galp5/devicetree.cb index aabeedb..3764d07 100644 --- a/src/mainboard/system76/galp5/devicetree.cb +++ b/src/mainboard/system76/galp5/devicetree.cb @@ -105,9 +105,7 @@
register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device ref dptf on - register "Device4Enable" = "1" - end + device ref dptf on end device ref peg on # PCIe PEG0 x4, Clock 0 (SSD1) register "PcieClkSrcUsage[0]" = "0x40" diff --git a/src/mainboard/system76/gaze16/devicetree.cb b/src/mainboard/system76/gaze16/devicetree.cb index f5f216c..8b43202 100644 --- a/src/mainboard/system76/gaze16/devicetree.cb +++ b/src/mainboard/system76/gaze16/devicetree.cb @@ -96,9 +96,7 @@ register "DdiPortBHpd" = "1" register "DdiPortBDdc" = "1" end - device ref dptf on - register "Device4Enable" = "1" - end + device ref dptf on end device ref gna on end device ref north_xhci on # TODO: No TBT, but needed for USB 2.0 on Type-C port? diff --git a/src/mainboard/system76/lemp10/devicetree.cb b/src/mainboard/system76/lemp10/devicetree.cb index 2c03e60..21928ec 100644 --- a/src/mainboard/system76/lemp10/devicetree.cb +++ b/src/mainboard/system76/lemp10/devicetree.cb @@ -105,9 +105,7 @@
register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device ref dptf on - register "Device4Enable" = "1" - end + device ref dptf on end device ref peg on # PCIe PEG0 x4, Clock 3 (SSD1) # Despite the name, SSD2_CLKREQ# is used for SSD1 diff --git a/src/mainboard/system76/oryp8/devicetree.cb b/src/mainboard/system76/oryp8/devicetree.cb index 4263806..e6372fd 100644 --- a/src/mainboard/system76/oryp8/devicetree.cb +++ b/src/mainboard/system76/oryp8/devicetree.cb @@ -110,9 +110,7 @@ register "DdiPortAHpd" = "1" register "DdiPortADdc" = "0" end - device ref dptf on - register "Device4Enable" = "1" - end + device ref dptf on end device ref peg0 on # PCIe PEG0 x4, Clock 7 (SSD1) register "PcieClkSrcUsage[7]" = "0x40" diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 09c8db1..fb0d827 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -274,8 +274,6 @@ /* Gfx related */ uint8_t SkipExtGfxScan;
- uint8_t Device4Enable; - /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 89c8126..40676f1 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -474,7 +474,7 @@ params->SlowSlewRate[0] = config->SlowSlewRate;
/* Enable TCPU for processor thermal control */ - params->Device4Enable = config->Device4Enable; + params->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF);
/* Set TccActivationOffset */ params->TccActivationOffset = config->tcc_offset;
5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one.