[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Disable CPU PCIe in FSP

[Shaunak Saha (Code Review)]

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )

Change subject: soc/intel/tigerlake: Disable CPU PCIe in FSP
......................................................................

Patch Set 5:

(9 comments)

https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@7 
PS3, Line 7: PCIE
> Will fix

Done

https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@9 
PS3, Line 9: iIn
> Will fix

Done

https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@9 
PS3, Line 9: Pcie
> Will fix

Done

https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@9 
PS3, Line 9: soc
> Will fix

Done

https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@10 
PS3, Line 10: Pcie
> Will fix

Done

https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@11 
PS3, Line 11: Pcie
> Will fix

Done

https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@18 
PS3, Line 18: this patch.
> Will fix

Done

https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... 
File src/soc/intel/tigerlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... 
PS3, Line 207: Pcie
> PCIe

Done

https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... 
PS3, Line 208: 0
> Thanks for the review. […]

Done