Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84124?usp=email )
Change subject: mb/google/brox/jubilant: Modify FP IRQ pin to GPP_D13 ......................................................................
mb/google/brox/jubilant: Modify FP IRQ pin to GPP_D13
Modify the FP IRQ pin to GPP_D13 from GPP_F15 from HW change on EVT. The design change to follow the brox's GPE0 routing, and the FP wake source can be routed.
BUG=b:363166664 TEST= Build jubilant firmware
Change-Id: Ic4a7ca07eab0dab234ab025cf77bbb8093b6b9d1 Signed-off-by: Ren Kuo ren.kuo@quanta.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/84124 Reviewed-by: Subrata Banik subratabanik@google.com Reviewed-by: Kenneth Chan kenneth.chan@quanta.corp-partner.google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/brox/variants/jubilant/gpio.c M src/mainboard/google/brox/variants/jubilant/overridetree.cb 2 files changed, 4 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Kenneth Chan: Looks good to me, approved Subrata Banik: Looks good to me, approved
diff --git a/src/mainboard/google/brox/variants/jubilant/gpio.c b/src/mainboard/google/brox/variants/jubilant/gpio.c index a8e652c..7562b65 100644 --- a/src/mainboard/google/brox/variants/jubilant/gpio.c +++ b/src/mainboard/google/brox/variants/jubilant/gpio.c @@ -40,8 +40,8 @@ PAD_CFG_GPO_LOCK(GPP_D3, 0, LOCK_CONFIG), /* GPP_D15 : ISH_UART0_RTS_L/I2C7B_SDA ==> FPMCU_RST_J_SUB_L (active low) */ PAD_CFG_GPO_LOCK(GPP_D15, 0, LOCK_CONFIG), - /* GPP_F15 : [NF1: GSXSRESET# NF3: THC1_SPI2_IO3 NF6: USB_C_GPP_F15] ==> FP GSPI INT */ - PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, PWROK, LEVEL, INVERT), + /* GPP_D13 : [NF1: ISH_UART0_RXD NF3: I2C6_SDA NF6: USB_C_GPP_D13] ==> FP GSPI INT */ + PAD_CFG_GPI_IRQ_WAKE(GPP_D13, NONE, PWROK, LEVEL, INVERT), /* GPP_F11 : [NF3: THC1_SPI2_CLK NF4: GSPI1_CLK NF6: USB_C_GPP_F11] ==> FP GSPI CLK */ PAD_CFG_NF_LOCK(GPP_F11, NONE, NF4, LOCK_CONFIG), /* GPP_F12 : [NF1: GSXDOUT NF3: THC1_SPI2_IO0 NF4: GSPI1_MOSI NF5: I2C1A_SCL diff --git a/src/mainboard/google/brox/variants/jubilant/overridetree.cb b/src/mainboard/google/brox/variants/jubilant/overridetree.cb index d1fbb8b..2f6f83b 100644 --- a/src/mainboard/google/brox/variants/jubilant/overridetree.cb +++ b/src/mainboard/google/brox/variants/jubilant/overridetree.cb @@ -399,8 +399,8 @@ register "hid" = "ACPI_DT_NAMESPACE_HID" register "uid" = "1" register "compat_string" = ""google,cros-ec-spi"" - register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" - register "wake" = "GPE0_DW2_15" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D13_IRQ)" + register "wake" = "GPE0_DW1_13" register "has_power_resource" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"