[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/braswell/include/soc/spi.h: Add OPTYPE values

[Frans Hendriks (Code Review)]

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31712

Change subject: soc/intel/braswell/include/soc/spi.h: Add OPTYPE values
......................................................................

soc/intel/braswell/include/soc/spi.h: Add OPTYPE values

Add SPI_OPTYPE_XXX values for the SPI controller.

BUG=N/A
TEST=flashrom on Facebook FBG-1701

Change-Id: Id183d68b3a80b2e7ab1a0685580d79ca327db03a
Signed-off-by: Frans Hendriks 
---
M src/soc/intel/braswell/include/soc/spi.h
1 file changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/31712/1

diff --git a/src/soc/intel/braswell/include/soc/spi.h b/src/soc/intel/braswell/include/soc/spi.h
index 49f3fcc..2d27545 100644
--- a/src/soc/intel/braswell/include/soc/spi.h
+++ b/src/soc/intel/braswell/include/soc/spi.h
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2013 Google Inc.
  * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2019 Eltan B.V.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -31,6 +32,10 @@
 # define DATA_CYCLE			(0x1 << 14)
 #define PREOP				0x94
 #define OPTYPE				0x96
+# define SPI_OPTYPE_RD_NOADDR		0x00	/* Read, no address */
+# define SPI_OPTYPE_WR_NOADDR		0x01	/* Write, no address */
+# define SPI_OPTYPE_RD_ADDR		0x02	/* Read, address required */
+# define SPI_OPTYPE_WR_ADDR		0x03	/* Write, address required */
 #define OPMENU0				0x98
 #define OPMENU1				0x9c
 #define LVSCC				0xc4