Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43277 )
Change subject: mb/mainboard/dedede: update GPIO table for Boten ......................................................................
Patch Set 6:
(7 comments)
https://review.coreboot.org/c/coreboot/+/43277/1/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/boten/gpio.c:
https://review.coreboot.org/c/coreboot/+/43277/1/src/mainboard/google/dedede... PS1, Line 9: pad_config gpio_table[]
Please use this CL: https://review.coreboot. […]
Done
https://review.coreboot.org/c/coreboot/+/43277/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/boten/gpio.c:
https://review.coreboot.org/c/coreboot/+/43277/2/src/mainboard/google/dedede... PS2, Line 10:
The blank line is not needed.
Done
https://review.coreboot.org/c/coreboot/+/43277/2/src/mainboard/google/dedede... PS2, Line 28:
If we don't use MIPI UCAM, GPIO E0 (CLK_24M_UCAM) can be NONE.
Done
https://review.coreboot.org/c/coreboot/+/43277/2/src/mainboard/google/dedede... PS2, Line 29: /* E2 : CLK_24M_WCAM */
The alignment of the colon is not helpful in my opinion. […]
I think it is done similar to other gpio.c files for consistency.
https://review.coreboot.org/c/coreboot/+/43277/2/src/mainboard/google/dedede... PS2, Line 42:
The blank line is not needed.
Done
https://review.coreboot.org/c/coreboot/+/43277/5/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/boten/gpio.c:
https://review.coreboot.org/c/coreboot/+/43277/5/src/mainboard/google/dedede... PS5, Line 18: PAD_CFG_GPO(GPP_D13, 1, PLTRST),
Yes,GPP_D13 be used for Camera enable pin.
My question was whether GPIO State 1 enables the camera or disables the camera. If GPIO state 1 is enabling the camera, do we need to enable it at the boot itself.
https://review.coreboot.org/c/coreboot/+/43277/5/src/mainboard/google/dedede... PS5, Line 34: /* E17 : HDMI_DDC_SCL */ : PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), : /* E18 : HDMI_DDC_SDA */ : PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
These 2 GPIOs are configured as required in the following coreboot CL: https://review.coreboot. […]
Done