Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80620?usp=email )
Change subject: mb/google/nissa/var/anraggar: Change tdp_pl1_override from 6 W to 15 W ......................................................................
mb/google/nissa/var/anraggar: Change tdp_pl1_override from 6 W to 15 W
Set tdp_pl1_override to 15 for performance required by the thermal team.
Fix policies.critical index from 2 to 0.
BUG=b:313833488 TEST=emerge-nissa coreboot
Change-Id: I5341bd3d4842f9298a2f5d9e589918bb1b06ba69 Signed-off-by: Weimin Wu wuweimin@huaqin.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/80620 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Subrata Banik subratabanik@google.com Reviewed-by: Eric Lai ericllai@google.com --- M src/mainboard/google/brya/variants/anraggar/overridetree.cb 1 file changed, 9 insertions(+), 2 deletions(-)
Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb index 0fd63a7..77ae2b6 100644 --- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb +++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb @@ -134,6 +134,13 @@ }, }"
+ # Power limit config + register "power_limits_config[ADL_N_041_6W_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 25, + .tdp_pl4 = 78, + }" + device domain 0 on device ref dtt on chip drivers/intel/dptf @@ -155,8 +162,8 @@
## Critical Policy register "policies.critical" = "{ - [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN), - [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN), + [0] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN), }"
register "controls.power_limits" = "{