Attention is currently required from: Cliff Huang, Kapil Porwal, Pranava Y N, Subrata Banik.
Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email )
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
......................................................................
Patch Set 45:
(2 comments)
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83798/comment/a5dea774_e5bf855c?usp... :
PS38, Line 401: endif
You mean to say, config "DROP_CPU_FEATURE_PROGRAM_IN_FSP" should be added?
Added.
File src/soc/intel/pantherlake/systemagent.c:
https://review.coreboot.org/c/coreboot/+/83798/comment/c2d7b04d_41d66178?usp... :
PS38, Line 165:
: /* Configure turbo power limits 1ms after reset complete bit */
: mdelay(1);
: config = config_of_soc();
:
: /* Get System Agent PCI ID */
: sa = pcidev_path_on_root(PCI_DEVFN_ROOT);
: sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF;
:
: /* Choose a power limits configuration based on the SoC SKU type,
: * differentiated here based on SA PCI ID. */
: switch (sa_pci_id) {
: case PCI_DID_INTEL_PTL_U_ID_1:
: case PCI_DID_INTEL_PTL_H_ID_1:
: case PCI_DID_INTEL_PTL_H_ID_2:
: soc_config = &config->power_limits_config[PTL_U_15W_POWER_LIMITS];
: break;
: default:
: printk(BIOS_ERR, "unknown SA ID: 0x%4x, skipping power limits configuration\n",
: sa_pci_id);
: return;
: }
:
: /* UPDATEME: Need to enable later */
: set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
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Updated based on ref. CL.
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