[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Update ACPI methods for CPU PCIe RPs

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Patrick Rudolph.
Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60183 )

Change subject: soc/intel/common/block/pcie/rtd3: Update ACPI methods for CPU PCIe RPs
......................................................................

soc/intel/common/block/pcie/rtd3: Update ACPI methods for CPU PCIe RPs

The PMC IPC method that is used for RTD3 support expects to be provided
the virtual wire index instead of the LCAP PN for CPU PCIe RPs. Therefore,
use the prior patches to update pcie_rp for CPU RPs.

BUG=b:197983574
TEST=add rtd3 node under pcie4_0 in overridetree for brya0, boot and
inspect the SSDT to see the PMC IPC parameters are as expected for the
CPU RP, and the ModPhy power gating code is not found in the AML for the
PEG port.

Signed-off-by: Tim Wawrzynczak 
Change-Id: I84a1affb32cb53e686dbe825d3c3a424715df873
---
M src/soc/intel/common/block/pcie/rtd3/rtd3.c
1 file changed, 20 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/60183/1

diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c
index 507c3c8..a23dbb8 100644
--- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c
+++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c
@@ -173,8 +173,7 @@
 }

static void
-pcie_rtd3_acpi_method_status(int pcie_rp,
-			     const struct soc_intel_common_block_pcie_rtd3_config *config)
+pcie_rtd3_acpi_method_status(const struct soc_intel_common_block_pcie_rtd3_config *config)
 {
    const struct acpi_gpio *gpio;

@@ -243,7 +242,7 @@
    	FIELDLIST_NAMESTR(ACPI_REG_PCI_L23_RDY_ENTRY, 1),
    	FIELDLIST_NAMESTR(ACPI_REG_PCI_L23_RDY_DETECT, 1),
    };
-	uint8_t pcie_rp;
+	int pcie_rp;
    struct acpi_dp *dsd, *pkg;

if (!is_dev_enabled(parent)) {
@@ -266,15 +265,25 @@
    }

const enum pcie_rp_type rp_type = soc_get_pcie_rp_type(parent);
-
-	/* Read port number of root port that this device is attached to. */
-	pcie_rp = pci_read_config8(parent, PCH_PCIE_CFG_LCAP_PN);
-	if (pcie_rp == 0 || pcie_rp > CONFIG_MAX_ROOT_PORTS) {
-		printk(BIOS_ERR, "%s: Invalid root port number: %u\n", __func__, pcie_rp);
+	if (rp_type == PCIE_RP_PCH) {
+		/* Read port number of root port that this device is attached to. */
+		pcie_rp = pci_read_config8(parent, PCH_PCIE_CFG_LCAP_PN);
+		if (pcie_rp == 0 || pcie_rp > CONFIG_MAX_ROOT_PORTS) {
+			printk(BIOS_ERR, "%s: Invalid root port number: %u\n", __func__, pcie_rp);
+			return;
+		}
+		/* Port number is 1-based, PMC IPC method expects 0-based. */
+		pcie_rp--;
+	} else if (rp_type == PCIE_RP_CPU) {
+		pcie_rp = soc_get_cpu_rp_vw_idx(parent);
+		if (pcie_rp < 0) {
+			printk(BIOS_ERR, "%s: Invalid CPU root port number\n", __func__);
+			return;
+		}
+	} else {
+		printk(BIOS_ERR, "%s: Unknown PCIe RP\n", __func__);
    	return;
    }
-	/* Port number is 1-based, PMC IPC method expects 0-based. */
-	pcie_rp--;

printk(BIOS_INFO, "%s: Enable RTD3 for %s (%s)\n", scope, dev_path(parent),
           config->desc ?: dev->chip_ops->name);
@@ -304,7 +313,7 @@

/* ACPI Power Resource for controlling the attached device power. */
    acpigen_write_power_res("RTD3", 0, 0, power_res_states, ARRAY_SIZE(power_res_states));
-	pcie_rtd3_acpi_method_status(pcie_rp, config);
+	pcie_rtd3_acpi_method_status(config);
    pcie_rtd3_acpi_method_on(pcie_rp, config, rp_type);
    pcie_rtd3_acpi_method_off(pcie_rp, config, rp_type);
    acpigen_pop_len(); /* PowerResource */