[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/cse: Implement HECI notify

[Subrata Banik (Code Review)]

Attention is currently required from: Arthur Heymans, Felix Singer, Tim Wawrzynczak, Sridhar Siricilla, Angel Pons, Patrick Rudolph, EricR Lai.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60405 )

Change subject: soc/intel/common/cse: Implement HECI notify
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Patch Set 15:

(1 comment)

File src/soc/intel/common/block/cse/cse_eop.c:

https://review.coreboot.org/c/coreboot/+/60405/comment/ce8dd192_ce4ebae2 
PS15, Line 246: send_end_of_post_to_cse
> As per ME BWG, BIOS should avoid sending EOP command during S3 resume. We should have check here to skip sending the EOP command. We can address it in separate CL.

@Sridhar, Please note two things 
1. This CL doesn't change the behaviour of sending EOP. It just add additional operations for lock config and D0i3.

2. Please take a look into https://github.com/coreboot/coreboot/blob/master/src/lib/hardwaremain.c#L195, ramstage boot state machine.

BS_PAYLOAD_BOOT and BS_PAYLOAD_LOAD states are not in scope of S3 resume. Upon S3 resume, the control will transfer to payload from BS_OS_RESUME /bs_os_resume () https://github.com/coreboot/coreboot/blob/master/src/lib/hardwaremain.c#L174 which is prior to BS_PAYLOAD_BOOT and BS_PAYLOAD_LOAD.

Hopefully, I'm able to clarify the basics of coreboot.