[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

[Patrick Rudolph (Code Review)]

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR
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Patch Set 8: Code-Review-1

According to https://github.com/tianocore/edk2/blob/master/UefiCpuPkg/Library/CpuCommonFe...
this should only be written on thread0 of each core. I've to check additional documentation, but it looks like this could #GP on HT enabled platforms.
This check should be done for all SoCs, for all MSR accesses in MP init.