Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/20058
Change subject: device/dram/ddr2.c: Fix is_registered_ddr2 ......................................................................
device/dram/ddr2.c: Fix is_registered_ddr2
Type 0x10 is mini RDIMM according to JEDEC DDR2 SPD specifications.
Change-Id: I6d35bd74961326ebd9225f044313b107aca24bda Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/device/dram/ddr2.c M src/include/device/dram/ddr2.h 2 files changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/20058/1
diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index 9eb3873..4d13f94 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -40,7 +40,8 @@ int spd_dimm_is_registered_ddr2(enum spd_dimm_type type) { if ((type == SPD_DIMM_TYPE_RDIMM) - | (type == SPD_DIMM_TYPE_72B_SO_RDIMM)) + || (type == SPD_DIMM_TYPE_72B_SO_RDIMM) + || (type == SPD_DIMM_TYPE_MINI_RDIMM)) return 1;
return 0; diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h index a752530..ea9b3ba 100644 --- a/src/include/device/dram/ddr2.h +++ b/src/include/device/dram/ddr2.h @@ -75,7 +75,7 @@ SPD_DIMM_TYPE_72B_SO_CDIMM = 0x06, SPD_DIMM_TYPE_72B_SO_RDIMM = 0x07, SPD_DIMM_TYPE_MICRO_DIMM = 0x08, - SPD_DIMM_TYPE_MINI_DIMM = 0x10, + SPD_DIMM_TYPE_MINI_RDIMM = 0x10, SPD_DIMM_TYPE_MINI_UDIMM = 0x20, /* Masks to bits 5:0 to give the dimm type */ SPD_DIMM_TYPE_MASK = 0x3f,