Attention is currently required from: Bao Zheng, Felix Held, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Matt DeVillier, Yu-Ping Wu.
Hello Bao Zheng, Felix Held, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Karthik Ramasubramanian, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83495?usp=email
to look at the new patch set (#5).
The following approvals got outdated and were removed: Code-Review+1 by Bao Zheng, Verified+1 by build bot (Jenkins)
Change subject: soc/amd: Ensure bank 0 is selected before accessing VBNV in CMOS ......................................................................
soc/amd: Ensure bank 0 is selected before accessing VBNV in CMOS
In AMD platforms, the bit 4 of CMOS's Register A (0x0a) is DV0 bank selection (0 for Bank 0; 1 for Bank 1) [1]. Since the MC146818 driver accesses VBNV via Bank 0, the bit must be cleared before we can save VBNV to CMOS in verstage.
Usually there's no problem with that, because the Register A is configured in cmos_init() in ramstage. However, if CMOS has lost power, then in the first boot after that, the bit may contain arbitrary data in verstage. If that bit happens to be 1, then CMOS writes in verstage will fail.
To fix the problem, define vbnv_platform_init_cmos() to call cmos_init(0), which will configure the Register A and therefore allow saving VBNV to CMOS in verstage.
[1] 48751_16h_bkdg.pdf
BUG=b:346716300 TEST=CMOS writes succeeded in verstage after battery cutoff BRANCH=skyrim
Change-Id: Idf167387b403be1977ebc08daa1f40646dd8c83f Signed-off-by: Yu-Ping Wu yupingso@chromium.org --- M src/soc/amd/common/vboot/vbnv_cmos.c 1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/83495/5