[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: add GPIO definitions for PCH-S

[Michał Kopeć (Code Review)]

Attention is currently required from: Michał Żygowski, Tim Wawrzynczak.
Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63467 )

Change subject: soc/intel/alderlake: add GPIO definitions for PCH-S
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Patch Set 1:

(1 comment)

File src/soc/intel/alderlake/include/soc/gpio_defs_pch_s.h:

https://review.coreboot.org/c/coreboot/+/63467/comment/0ab05dd3_aa6e8423 
PS1, Line 288: #define GPP_F20_IRQ	0x70
             : #define GPP_F21_IRQ	0x71
             : #define GPP_F22_IRQ	0x72
             : #define GPP_F23_IRQ	0x73
             : 
             : /* Group D */
             : #define GPP_D0_IRQ	0x70
             : #define GPP_D1_IRQ	0x71
             : #define GPP_D2_IRQ	0x72
             : #define GPP_D3_IRQ	0x73
> is this really the way they overlap, seems odd, would expect it to start over from 0x18 like D8 does […]

hmm, that's what doc #621483 says