Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9509
-gerrit
commit a758a7107a9f11e6cb338f723c9800b7348f1f6b Author: Kane Chen kane.chen@intel.com Date: Thu Feb 12 16:08:42 2015 +0800
baytrail: correct NC pin to GPO pin according to BYT platform design guide
According to BYT platform design guide chap 14.2.2, the NC GPIOs need to be configured to GPO.
BRANCH=none BUG=none TEST=Test on rambi, boot to OS, and make sure NC pins config to GPO
Change-Id: Ida5ea89ee66e39b4fddea242dc918b314756d94f Signed-off-by: Stefan Reinauer reinauer@chromium.org Original-Commit-Id: 998493566f5cf7abd9375583e12fe631b226e591 Original-Change-Id: Ieaf346d1c7bf3ecb47a71a6ee4afaa805235cc37 Original-Signed-off-by: Kane Chen kane.chen@intel.com Original-Reviewed-on: https://chromium-review.googlesource.com/249060 Original-Reviewed-by: Aaron Durbin adurbin@chromium.org --- src/soc/intel/baytrail/include/soc/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h index 413ade2..f312cdc 100644 --- a/src/soc/intel/baytrail/include/soc/gpio.h +++ b/src/soc/intel/baytrail/include/soc/gpio.h @@ -322,7 +322,7 @@ #define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU #define GPIO_INPUT_PU GPIO_INPUT_PU_20K #define GPIO_INPUT_PD GPIO_INPUT_PD_20K -#define GPIO_NC GPIO_INPUT_PU_20K +#define GPIO_NC GPIO_OUT_HIGH #define GPIO_DEFAULT GPIO_FUNC0
/* 16 DirectIRQs per supported bank */