Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31445
Change subject: soc/intel/cannonlake: Add a power control workaround for SD controller ......................................................................
soc/intel/cannonlake: Add a power control workaround for SD controller
SD_VDD1_PWR_EN# does not de-assert during SDXC D3 or when SD card is not inserted. For platforms using SD_VDD1_PWR_EN# as active high, the SDXC card connector is always powered and may impact system power.
Workaround is to change the pad ownership of SD_VDD1_PWR_EN to GPIO and force the TX buffer to low in _PS3. And restore the pad mode to native funtion in _PS0.
Also add a Kconfig option to allow a mainboard to choose if this workaround is required, based on how the SD_VDD1_PWR_EN is implemented on it.
BUG=b:123350329
Change-Id: Iee262d7ecdf8c31362aec3d95dd9b3e8359e0c25 Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/acpi/scs.asl M src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h 3 files changed, 23 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/31445/1
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index bacbe7b..dce116b 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -236,6 +236,14 @@ hex default 0x200000
+config MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE + bool "Activate workaround in ASL for keeping SD_PWR_ENABLE low in D3" + default n + help + Select this if the board has a SD_PWR_ENABLE pin connected to a + active high sensing load switch to turn on power to the card reader. + This will enable a workaround in ASL _PS3 and _PS0 methods to force + SD_PWR_ENABLE to stay low in D3. choice prompt "Cache-as-ram implementation" default USE_CANNONLAKE_CAR_NEM_ENHANCED if MAINBOARD_HAS_CHROMEOS diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index 896fd77..558d538 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -111,6 +111,11 @@ /* Set Power State to D0 */ And (PMCR, 0xFFFC, PMCR) Store (PMCR, ^TEMP) + +#if IS_ENABLED(CONFIG_MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) + /* Change pad mode to Native*/ + GPMO(SD_PWR_EN_PIN, 0x1) +#endif }
Method (_PS3, 0, Serialized) @@ -120,6 +125,14 @@ /* Set Power State to D3 */ Or (PMCR, 0x0003, PMCR) Store (PMCR, ^TEMP) + +#if IS_ENABLED(CONFIG_MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) + /* Change pad mode to GPIO control */ + GPMO(SD_PWR_EN_PIN, 0x0) + + /* Drive TX to zero */ + CTXS(SD_PWR_EN_PIN) +#endif }
Device (CARD) diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h index cb184c9..380ec66 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h @@ -352,4 +352,6 @@ #define NUM_GPIO_COM3_PADS (GPIO_RSVD_78 - HDA_BCLK + 1)
#define TOTAL_PADS 275 + +#define SD_PWR_EN_PIN GPP_A17 #endif