[coreboot-gerrit] [XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage

[Saurabh Mishra (Code Review)]

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik.

Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email )

Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
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Patch Set 61:

(1 comment)

File src/soc/intel/pantherlake/cpu.c:

https://review.coreboot.org/c/coreboot/+/83798/comment/ccfa82a7_15cbc29c?usp... :
PS50, Line 143: disable_three_strike_error
> > Hi Subrata, we can take up this as a TODO. […]

Hi Subrata, EDS 2 has a (DISABLE_SIGNALING_THREE_STRIKE_EVENT) – Offset 1ab.

as pointed, disable_signaling_three_strike_event should be used, correct?