[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43980 )

Change subject: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms
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Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/43980/2/src/soc/intel/tigerlake/fsp... 
File src/soc/intel/tigerlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/43980/2/src/soc/intel/tigerlake/fsp... 
PS2, Line 119: 	cpu_id = cpu_get_cpuid();
             : 	if (cpu_id == CPUID_TIGERLAKE_A0)
             : 		params->D3ColdEnable = 0;
             : 	else
> we have dedicated variants for ES2 vs. QS SoCs - i.e. A0 vs. B0 silicon. […]

As this is only A0 limitaion, I think it's better handle by devicetree rather than soc code change.