[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Correct TCSS XHCI Port status offset

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Balaji Manigandan, Deepti Deshatty, Patrick Rudolph.
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55230 )

Change subject: soc/intel/alderlake: Correct TCSS XHCI Port status offset
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Patch Set 2:

(1 comment)

File src/soc/intel/alderlake/xhci.c:

https://review.coreboot.org/c/coreboot/+/55230/comment/b3d22fc4_6fbcc30c 
PS1, Line 19: 10
This needs correction as well since ADL-P CPU doesn't support USB2 ports. For CPU TCSS ports support, PCH USB2 ports are used.