Aaron Durbin (adurbin@chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9438
-gerrit
commit e6eb18b8086ff8930315bd0b54aa1099acfe16f0 Author: David Hendricks dhendrix@chromium.org Date: Mon Nov 3 17:42:09 2014 -0800
cbtables: Add RAM config information
This adds the RAM config code to the coreboot tables. The purpose is to expose this information to software running at higher levels, e.g. to print the RAM config coreboot is using as part of factory tests.
The prototype for ram_code() is in boardid.h since they are closely related and will likely have common code.
BUG=chrome-os-partner:31728 BRANCH=none TEST=tested w/ follow-up CLs on pinky
Original-Signed-off-by: David Hendricks dhendrix@chromium.org Original-Change-Id: Idd38ec5b6af16e87dfff2e3750c18fdaea604400 Original-Reviewed-on: https://chromium-review.googlesource.com/227248 Original-Reviewed-by: Julius Werner jwerner@chromium.org
(cherry picked from commit 77dd5fb9347b53bb8a64ad22341257fb3be0c106) Signed-off-by: Aaron Durbin adurbin@chromium.org
Change-Id: Ibe7044cafe0a61214ac2d7fea5f7255b2c11829b --- src/Kconfig | 7 +++++++ src/include/boardid.h | 1 + src/include/boot/coreboot_tables.h | 7 +++++++ src/lib/coreboot_table.c | 16 ++++++++++++++++ 4 files changed, 31 insertions(+)
diff --git a/src/Kconfig b/src/Kconfig index f94fad4..5cc5485 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -253,6 +253,13 @@ config UPDATE_IMAGE is a suitable file for further processing. The bootblock will not be modified.
+config RAM_CODE_SUPPORT + bool "Discover RAM configuration code and store it in coreboot table" + default n + help + If enabled, coreboot discovers RAM configuration (value obtained by + reading board straps) and stores it in coreboot table. + endmenu
source "src/mainboard/Kconfig" diff --git a/src/include/boardid.h b/src/include/boardid.h index d1c6ad9..41c21d6 100644 --- a/src/include/boardid.h +++ b/src/include/boardid.h @@ -23,5 +23,6 @@ #include <stdint.h>
uint8_t board_id(void); +uint32_t ram_code(void);
#endif /* __INCLUDE_BOARDID_H__ */ diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 0efb8fd..d9df787 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -276,6 +276,13 @@ struct lb_macs { struct mac_address mac_addrs[0]; };
+#define LB_TAG_RAM_CODE 0x0028 +struct lb_ram_code { + uint32_t tag; + uint32_t size; + uint32_t ram_code; +}; + /* The following structures are for the cmos definitions table */ #define LB_TAG_CMOS_OPTION_TABLE 200 /* cmos header record */ diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index a8b5edf..a514bb9 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -297,6 +297,19 @@ static void lb_board_id(struct lb_header *header) #endif }
+static void lb_ram_code(struct lb_header *header) +{ +#if IS_ENABLED(CONFIG_RAM_CODE_SUPPORT) + struct lb_ram_code *code; + + code = (struct lb_ram_code *)lb_new_record(header); + + code->tag = LB_TAG_RAM_CODE; + code->size = sizeof(*code); + code->ram_code = ram_code(); +#endif +} + static void add_cbmem_pointers(struct lb_header *header) { /* @@ -525,6 +538,9 @@ unsigned long write_coreboot_table( /* Add board ID if available */ lb_board_id(head);
+ /* Add RAM config if available */ + lb_ram_code(head); + add_cbmem_pointers(head);
/* Add board-specific table entries, if any. */