Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44711 )
Change subject: soc/mediatek/mt8192: Add DDR mode register init
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Patch Set 52:
(3 comments)
https://review.coreboot.org/c/coreboot/+/44711/50/src/soc/mediatek/mt8192/dr...
File src/soc/mediatek/mt8192/dramc_dvfs.c:
https://review.coreboot.org/c/coreboot/+/44711/50/src/soc/mediatek/mt8192/dr...
PS50, Line 23: = 0
No need to initialize. Or we may write: […]
Done
https://review.coreboot.org/c/coreboot/+/44711/50/src/soc/mediatek/mt8192/dr...
PS50, Line 85: wait shu_en ack.
Waiting shu_en ack […]
Ack
https://review.coreboot.org/c/coreboot/+/44711/50/src/soc/mediatek/mt8192/dr...
PS50, Line 102: complete
completed
Ack
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Gerrit-Project: coreboot
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Gerrit-Change-Id: If200f4dcef0b1d0b7e901d4ae6e667b1f75156f5
Gerrit-Change-Number: 44711
Gerrit-PatchSet: 52
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