[coreboot-gerrit] Change in coreboot[master]: soc/intel/cmn/fast_spi: Add API to clear outstanding SPI status

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63625 )

Change subject: soc/intel/cmn/fast_spi: Add API to clear outstanding SPI status
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Patch Set 6:

(1 comment)

File src/soc/intel/common/block/fast_spi/fast_spi.c:

https://review.coreboot.org/c/coreboot/+/63625/comment/875c1688_35debe4c 
PS6, Line 437: SPIBAR_HSFSTS_W1C_BITS
> I must admitt that Elkhart Lake does define bit 8 as well. Sorry for overseeing it.

how about making is a word width ? actually BIOS_HSFSTS_CTL (offset 0x4) has two part as in LSB is HSFSTS and MSB is HSFCTL. In that case 0xFFFF would serve best IMO.

WDYT?