[coreboot-gerrit] Change in coreboot[master]: sb/intel/bd82x6x: Add addtional SPI register

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded a new change for review. ( https://review.coreboot.org/19493 )

Change subject: sb/intel/bd82x6x: Add addtional SPI register
......................................................................

sb/intel/bd82x6x: Add addtional SPI register

Add AFC—Additional Flash Control Register to be used
with devicetree.

Change-Id: I627082e09dd055e3b3c4dd8e0b90965a9fcb4342
Signed-off-by: Patrick Rudolph 
---
M src/southbridge/intel/bd82x6x/chip.h
M src/southbridge/intel/bd82x6x/lpc.c
2 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/19493/1

diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index e1064a7..948bbca 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -95,6 +95,7 @@

uint32_t spi_uvscc;
    uint32_t spi_lvscc;
+	uint32_t spi_afc;
 };

#endif				/* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 623482e..89e3f12 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -496,6 +496,8 @@
    	RCBA32(0x3800 + 0xc8) = config->spi_uvscc;
    if (config->spi_lvscc)
    	RCBA32(0x3800 + 0xc4) = config->spi_lvscc;
+	if (config->spi_afc)
+		RCBA32(0x3800 + 0xc0) = config->spi_afc;

if (config->spi_uvscc || config->spi_lvscc)
    	RCBA32_OR(0x3800 + 0xc4, 1 << 23); /* lock both UVSCC + LVSCC */