[coreboot-gerrit] New patch to review for coreboot: abce7ed broadwell: Remove XHCI workarounds on WPT

[Stefan Reinauer]

Stefan Reinauer ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9488

-gerrit

commit abce7ed8787c880df696bb86fde7507b27ea697d
Author: Duncan Laurie 
Date:   Wed Jan 14 12:18:46 2015 -0800

broadwell: Remove XHCI workarounds on WPT

The workarounds in ACPI methods for D0/D3 transition that are
    used on haswell/LPT do not all apply to broadwell/WPT.

BUG=chrome-os-partner:28234
    BRANCH=broadwell
    TEST=build and boot on samus, test USB functionality and wake
    and ensure the device still does into D3 state

Change-Id: Ic3a75f5bf50e826ade7d942b48cfebb75cf976e6
    Signed-off-by: Stefan Reinauer 
    Original-Commit-Id: 1b54d105957ee80ca34048c42fb8f241731281cf
    Original-Change-Id: I877afd51fc6c9b7906e923b893fc31bdf2cd1090
    Original-Signed-off-by: Duncan Laurie 
    Original-Reviewed-on: https://chromium-review.googlesource.com/240850
    Original-Reviewed-by: Shawn N 
---
 src/soc/intel/broadwell/acpi/xhci.asl | 68 +++++++++++++++++++++++------------
 1 file changed, 46 insertions(+), 22 deletions(-)

diff --git a/src/soc/intel/broadwell/acpi/xhci.asl b/src/soc/intel/broadwell/acpi/xhci.asl
index 9d870e5..c41275c 100644
--- a/src/soc/intel/broadwell/acpi/xhci.asl
+++ b/src/soc/intel/broadwell/acpi/xhci.asl
@@ -35,6 +35,14 @@ Device (XHCI)
    	Offset (0x10),
    	, 16,
    	XMEM, 16, // MEM_BASE
+		Offset (0x40),
+		, 11,
+		SWAI, 1,
+		, 20,
+		Offset (0x44),
+		, 12,
+		SAIP, 2,
+		, 18,
    	Offset (0x74),
    	D0D3, 2,
    	, 6,
@@ -242,22 +250,30 @@ Device (XHCI)
    		Store (0, ^D0D3)
    	}

-		// Clear PCI 0xB0[14:13]
-		Store (0, ^MB13)
-		Store (0, ^MB14)
+		if (LNot (\ISWP())) {
+			// Clear PCI 0xB0[14:13]
+			Store (0, ^MB13)
+			Store (0, ^MB14)

-		// Clear MMIO 0x816C[14,2]
-		Store (0, CLK0)
-		Store (0, CLK1)
+			// Clear MMIO 0x816C[14,2]
+			Store (0, CLK0)
+			Store (0, CLK1)

-		// Set MMIO 0x8154[31]
-		Store (1, CLK2)
+			// Set MMIO 0x8154[31]
+			Store (1, CLK2)

-		// Handle per-port reset if needed
-		LPS0 ()
+			// Handle per-port reset if needed
+			LPS0 ()

-		// Set MMIO 0x80e0[15]
-		Store (1, AX15)
+			// Set MMIO 0x80e0[15]
+			Store (1, AX15)
+
+			// Clear PCI CFG offset 0x40[11]
+			Store (0, ^SWAI)
+
+			// Clear PCI CFG offset 0x44[13:12]
+			Store (0, ^SAIP)
+		}

Return ()
    }
@@ -297,19 +313,27 @@ Device (XHCI)
    		Store (0, ^D0D3)
    	}

-		// Set PCI 0xB0[14:13]
-		Store (1, ^MB13)
-		Store (1, ^MB14)
+		if (LNot (\ISWP())) {
+			// Set PCI 0xB0[14:13]
+			Store (1, ^MB13)
+			Store (1, ^MB14)

-		// Set MMIO 0x816C[14,2]
-		Store (1, CLK0)
-		Store (1, CLK1)
+			// Set MMIO 0x816C[14,2]
+			Store (1, CLK0)
+			Store (1, CLK1)

-		// Clear MMIO 0x8154[31]
-		Store (0, CLK2)
+			// Clear MMIO 0x8154[31]
+			Store (0, CLK2)

-		// Clear MMIO 0x80e0[15]
-		Store (0, AX15)
+			// Clear MMIO 0x80e0[15]
+			Store (0, AX15)
+
+			// Set PCI CFG offset 0x40[11]
+			Store (1, ^SWAI)
+
+			// Set PCI CFG offset 0x44[13:12]
+			Store (1, ^SAIP)
+		}

// Put device in D3
    	Store (3, ^D0D3)