Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Jérémy Compostella, Paul Menzel, Saurabh Mishra, Wonkyu Kim.
Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83981?usp=email )
Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID and fix vw mapping ......................................................................
Patch Set 5:
(2 comments)
File src/soc/intel/common/block/gpio/Kconfig:
https://review.coreboot.org/c/coreboot/+/83981/comment/f3b4d903_dbad38a6?usp... : PS5, Line 66: config SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID : bool : default n : help : In newer SOC, port ID has been extended to 16-bit. This must be set to accommodate : the structure to hold the 16-bit value. : ``` config SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID bool default n help Enable support for 16-bit CPU Port IDs.
Intel SoCs (starting with Panther Lake) have extended the CPU Port ID field to 16 bits. Enable this option if your platform requires the GPIO driver to accommodate this larger Port ID value. ```
File src/soc/intel/common/block/include/intelblocks/gpio.h:
https://review.coreboot.org/c/coreboot/+/83981/comment/bd4adcdc_52b8d16b?usp... : PS5, Line 113: /* virtual-wire mapping base and the starting bit position for a group */ : struct vw_map { : uint8_t base; : uint8_t start_pos; : }; keep this part of the vw cl