[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Disable CPU PCIE in FSP

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )

Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP
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Patch Set 3:

(4 comments)

https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@10 
PS3, Line 10: Pcie
PCIe

https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@11 
PS3, Line 11: Pcie
PCIe

https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@11 
PS3, Line 11: hence saves ~30ms in
            : FspSiliconInit.
Nice!

https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@18 
PS3, Line 18: this patch.
Fits on the line above?