Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/26943
Change subject: soc/intel/{skl,cnl,apl}: Move common UART code to common block ......................................................................
soc/intel/{skl,cnl,apl}: Move common UART code to common block
Move common UART related function to common block instead of keeping it inside each soc folder. This will reduce redundant function across all soc.
BUG=none BRANCH=none TEST=code compiles fine for all platfrom
Change-Id: Ia583262d07e1c1ed2105fed25fbd5c8adb07c994 Signed-off-by: Maulik V Vaghela maulik.v.vaghela@intel.com --- M src/soc/intel/apollolake/bootblock/bootblock.c D src/soc/intel/apollolake/include/soc/uart.h M src/soc/intel/apollolake/romstage.c M src/soc/intel/apollolake/uart.c M src/soc/intel/cannonlake/bootblock/bootblock.c M src/soc/intel/cannonlake/include/soc/pch.h M src/soc/intel/cannonlake/uart.c M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/common/block/uart/uart.c M src/soc/intel/skylake/bootblock/bootblock.c M src/soc/intel/skylake/include/soc/bootblock.h M src/soc/intel/skylake/uart.c 12 files changed, 92 insertions(+), 114 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/26943/1
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 392237f..85baf5b 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -24,13 +24,13 @@ #include <intelblocks/rtc.h> #include <intelblocks/systemagent.h> #include <intelblocks/pmclib.h> +#include <intelblocks/uart.h> #include <soc/iomap.h> #include <soc/cpu.h> #include <soc/gpio.h> #include <soc/systemagent.h> #include <soc/pci_devs.h> #include <soc/pm.h> -#include <soc/uart.h> #include <spi-generic.h> #include <timestamp.h>
diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h deleted file mode 100644 index bf8b9d7..0000000 --- a/src/soc/intel/apollolake/include/soc/uart.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Intel Corp. - * (Written by Alexandru Gagniuc alexandrux.gagniuc@intel.com for Intel Corp.) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_APOLLOLAKE_UART_H_ -#define _SOC_APOLLOLAKE_UART_H_ - -/* Initialize the console UART including the pads for the configured UART. */ -void pch_uart_init(void); - -#endif /* _SOC_APOLLOLAKE_UART_H_ */ diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 1a25105..4168771 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -47,7 +47,6 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> -#include <soc/uart.h> #include <spi_flash.h> #include <string.h> #include <timestamp.h> diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index f9a4c8b..27f79e1 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -21,12 +21,10 @@ */
#include <console/uart.h> -#include <device/device.h> #include <device/pci.h> #include <intelblocks/uart.h> #include <soc/gpio.h> #include <soc/pci_devs.h> -#include <soc/uart.h>
static const struct pad_config uart_gpios[] = { #if IS_ENABLED(CONFIG_SOC_INTEL_GLK) @@ -46,20 +44,18 @@ #endif };
-void pch_uart_init(void) +const struct pad_config *soc_get_gpio_pad(uint8_t pad_index) { - uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS; - device_t uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3); + /* + * For APL, we have UART1 and UART2 valid. + * Making an index 0 based for an array + */ + uint8_t array_index = pad_index - 1;
- /* Get a 0-based pad index. See invalid_uart_for_console() above. */ - const int pad_index = CONFIG_UART_FOR_CONSOLE - 1; + if ((array_index * 2) < sizeof(uart_gpios)) + return &uart_gpios[array_index * 2];
- /* Configure the 2 pads per UART. */ - gpio_configure_pads(&uart_gpios[pad_index * 2], 2); - - /* Program UART2 BAR0, command, reset and clock register */ - uart_common_init(uart, base); - + die("Invalid UART console index selected for soc"); }
uintptr_t uart_platform_base(int idx) diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index b7e7797..ad18696 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -15,6 +15,7 @@
#include <bootblock_common.h> #include <intelblocks/gspi.h> +#include <intelblocks/uart.h> #include <soc/bootblock.h> #include <soc/iomap.h> #include <soc/pch.h> diff --git a/src/soc/intel/cannonlake/include/soc/pch.h b/src/soc/intel/cannonlake/include/soc/pch.h index 53dd66a..da64a7a8 100644 --- a/src/soc/intel/cannonlake/include/soc/pch.h +++ b/src/soc/intel/cannonlake/include/soc/pch.h @@ -29,6 +29,5 @@ #define PCIE_CLK_FREE 0x80
void pch_log_state(void); -void pch_uart_init(void);
#endif diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c index 6babe61..70657ac 100644 --- a/src/soc/intel/cannonlake/uart.c +++ b/src/soc/intel/cannonlake/uart.c @@ -30,49 +30,23 @@ #define PCR_SERIAL_IO_GPPRVRW7 0x618 #define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx))
-static const struct port { - struct pad_config pads[2]; /* just TX and RX */ - device_t dev; -} uart_ports[] = { - {.dev = PCH_DEV_UART0, - .pads = { PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* RX */ - PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1)} /* TX */ - }, - {.dev = PCH_DEV_UART1, - .pads = { PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* RX */ - PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1)} /* TX */ - }, - {.dev = PCH_DEV_UART2, - .pads = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* RX */ - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1)} /* TX */ - } +static const struct pad_config uart_gpios[] = { + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /*UART0 RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /*UART0 TX */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /*UART1 RX */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /*UART1 TX */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /*UART2 RX */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1) /*UART2 TX */ };
-void pch_uart_init(void) +const struct pad_config *soc_get_gpio_pad(uint8_t pad_index) { - uintptr_t base; - const struct port *p; + if ((pad_index * 2) < sizeof(uart_gpios)) + return &uart_gpios[pad_index * 2];
- assert(CONFIG_UART_FOR_CONSOLE < ARRAY_SIZE(uart_ports)); - p = &uart_ports[CONFIG_UART_FOR_CONSOLE]; - base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); - - uart_common_init(p->dev, base); - - /* Put UART2 in byte access mode for 16550 compatibility */ - if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) { - pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7, - PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE)); - - /* - * Dummy read after setting any of GPPRVRW7. - * Required for UART 16550 8-bit Legacy mode to become active - */ - lpss_clk_read(base); - } - - gpio_configure_pads(p->pads, ARRAY_SIZE(p->pads)); + die("Invalid UART console index for soc"); } + #endif
#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM) diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h index 2734810..653918f 100644 --- a/src/soc/intel/common/block/include/intelblocks/uart.h +++ b/src/soc/intel/common/block/include/intelblocks/uart.h @@ -44,6 +44,10 @@ */ bool uart_is_debug_controller(struct device *dev);
+/* + * BootBlock pre initialization of UART console + */ +void pch_uart_init(void); /**************************** SoC callbacks ***********************************/
void pch_uart_read_resources(struct device *dev); @@ -61,6 +65,18 @@ device_t soc_uart_console_to_device(uint8_t uart_console);
/* + * Get GPIO configuration pad for UART console + * + * Input: + * UART console index selected in config + * + * Returns: + * Pointer to pad_config structure if valid UART index + * NULL = otherwise + */ +const struct pad_config *soc_get_gpio_pad(uint8_t pad_index); + +/* * Get UART debug controller device structure * * Returns: diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 1717cd6..dd14e3a 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -17,19 +17,27 @@ #include <assert.h> #include <compiler.h> #include <cbmem.h> +#include <console/uart.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <intelblocks/gpio.h> #include <intelblocks/lpss.h> +#include <intelblocks/pcr.h> #include <intelblocks/uart.h> #include <soc/pci_devs.h> #include <soc/iomap.h> #include <soc/nvs.h> +#include <soc/pcr_ids.h>
#define UART_PCI_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)
+/* Serial IO UART controller legacy mode */ +#define PCR_SERIAL_IO_GPPRVRW7 0x618 +#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx)) + static void uart_lpss_init(uintptr_t baseaddr) { /* Take UART out of reset */ @@ -90,6 +98,35 @@ return !lpss_is_controller_in_reset(base); }
+void pch_uart_init(void) +{ + uintptr_t base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + device_t uart = pch_uart_get_device(); + const struct pad_config *uart_gpios = soc_get_gpio_pad( + CONFIG_UART_FOR_CONSOLE); + + /* Program UART2 BAR0, command, reset and clock register */ + uart_common_init(uart, base); + +#if (!IS_ENABLED(CONFIG_SOC_INTEL_APOLLOLAKE)) + /* Put UART2 in byte access mode for 16550 compatibility */ + if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) { + pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7, + PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE)); + + /* + * Dummy read after setting any of GPPRVRW7. + * Required for UART 16550 8-bit Legacy mode to become active + */ + lpss_clk_read(base); + } +#endif + + /* Configure the 2 pads per UART. */ + gpio_configure_pads(uart_gpios, 2); +} + + #if ENV_RAMSTAGE
void pch_uart_read_resources(struct device *dev) diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index 1803694..34d3f7a 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -16,6 +16,7 @@ #include <bootblock_common.h> #include <drivers/i2c/designware/dw_i2c.h> #include <intelblocks/gspi.h> +#include <intelblocks/uart.h> #include <soc/bootblock.h>
asmlinkage void bootblock_c_entry(uint64_t base_timestamp) diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index 59ce92a..f506514 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -27,7 +27,6 @@ /* Bootblock pre console init programming */ void bootblock_cpu_init(void); void bootblock_pch_early_init(void); -void pch_uart_init(void);
/* Bootblock post console init programming */ void i2c_early_init(void); diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c index 945a0a0..703ed36 100644 --- a/src/soc/intel/skylake/uart.c +++ b/src/soc/intel/skylake/uart.c @@ -30,21 +30,23 @@ #define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx))
/* UART pad configuration. Support RXD and TXD for now. */ -static const struct pad_config uart_pads[][2] = { - { - PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ - PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ - }, - { - PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1_RXD */ - PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1_TXD */ - }, - { - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */ - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */ - } +static const struct pad_config uart_gpios[] = { + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1_RXD */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1_TXD */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */ };
+struct pad_config *soc_get_gpio_pad(uint8_t pad_index) +{ + if ((pad_index * 2) < sizeof(uart_gpios)) + return &uart_gpios[pad_index * 2]; + + die("Invalid UART console index for soc"); +} + #if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM) uintptr_t uart_platform_base(int idx) { @@ -54,28 +56,6 @@ } #endif
-void pch_uart_init(void) -{ - uintptr_t base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); - - uart_common_init(pch_uart_get_device(), base); - - /* Put UART in byte access mode for 16550 compatibility */ - if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) { - pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7, - PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE)); - - /* - * Dummy read after setting any of GPPRVRW7. - * Required for UART 16550 8-bit Legacy mode to become active - */ - lpss_clk_read(base); - } - - gpio_configure_pads(uart_pads[CONFIG_UART_FOR_CONSOLE], - ARRAY_SIZE(uart_pads[CONFIG_UART_FOR_CONSOLE])); -} - device_t soc_uart_console_to_device(uint8_t uart_console) { /*