[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Modify CSE's PCI BAR address

[Sridhar Siricilla (Code Review)]

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44211 )

Change subject: soc/intel/cannonlake: Modify CSE's PCI BAR address
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soc/intel/cannonlake: Modify CSE's PCI BAR address

The patch modifies CSE's PCI BAR address to 0xfed1a000. Currently coreboot
uses 0xfeda2000 as a PCI BAR address for CSE device while FSP-M uses
0xfed1a000. So, after FSP-M call, CSE's BAR address is overridden with
0xfed1a000. This causes HECI command transactions fail between FSP-M call
and postcar.

TEST=Verified sending HECI commands before and after FSP-M call on hatch.

Signed-off-by: Sridhar Siricilla 
Change-Id: I371cb658a96f5d580faff32ffab013cb6e6c492c
---
M src/soc/intel/cannonlake/include/soc/iomap.h
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/44211/1

diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h
index dc07089..9a58c65 100644
--- a/src/soc/intel/cannonlake/include/soc/iomap.h
+++ b/src/soc/intel/cannonlake/include/soc/iomap.h
@@ -52,7 +52,11 @@

#define GPIO_BASE_SIZE		0x10000

+#if CONFIG(SOC_INTEL_COMETLAKE)
+#define HECI1_BASE_ADDRESS	0xfed1a000
+#else
 #define HECI1_BASE_ADDRESS	0xfeda2000
+#endif

/* PTT registers */
 #define PTT_TXT_BASE_ADDRESS	0xfed30800