[coreboot-gerrit] Change in coreboot[master]: mb/google/brya/variants/gimble: Fix GL9750S SD card reader power sequ...

[Scott Chao (Code Review)]

Scott Chao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56898 )

Change subject: mb/google/brya/variants/gimble: Fix GL9750S SD card reader power sequence
......................................................................

mb/google/brya/variants/gimble: Fix GL9750S SD card reader power sequence

- Enable EN_PP3300_SD
- Configure SD_PE_RST_L correctly

BUG=b:196021879
TEST=Able to boot with SD card

Signed-off-by: Scott Chao 
Change-Id: I7d2fe8512696879936347fa8391aac21d7c17e31
---
M src/mainboard/google/brya/variants/gimble/gpio.c
1 file changed, 5 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/56898/1

diff --git a/src/mainboard/google/brya/variants/gimble/gpio.c b/src/mainboard/google/brya/variants/gimble/gpio.c
index d47c732..6f456b0 100644
--- a/src/mainboard/google/brya/variants/gimble/gpio.c
+++ b/src/mainboard/google/brya/variants/gimble/gpio.c
@@ -49,6 +49,8 @@
    PAD_NC(GPP_D15, NONE),
    /* D17 : UART1_RXD ==> NC */
    PAD_NC(GPP_D17, NONE),
+	/* D18 : UART1_TXD ==> SD_PE_RST_L */
+	PAD_CFG_GPO(GPP_D18, 1, PLTRST),

/* E0  : SATAXPCIE0 ==> NC */
    PAD_NC(GPP_E0, NONE),
@@ -124,6 +126,8 @@
    PAD_CFG_GPO(GPP_D1, 0, DEEP),
    /* D2  : ISH_GP2 ==> EN_FP_PWR */
    PAD_CFG_GPO(GPP_D2, 1, DEEP),
+	/* D18 : UART1_TXD ==> SD_PE_RST_L */
+	PAD_CFG_GPO(GPP_D18, 0, PLTRST),
    /* E0  : SATAXPCIE0 ==> NC */
    PAD_NC(GPP_E0, NONE),
    /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
@@ -137,7 +141,7 @@
    /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
    PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
    /* H13 : I2C7_SCL ==> EN_PP3300_SD */
-	PAD_NC(GPP_H13, UP_20K),
+	PAD_CFG_GPO(GPP_H13, 1, PLTRST),
 };

const struct pad_config *variant_gpio_override_table(size_t *num)