the following patch was just integrated into master: commit 83067610f754f89025bf781cdf8857135e946b03 Author: Wenkai Du wenkai.du@intel.com Date: Fri Dec 5 14:00:26 2014 -0800
broadwell: Fix PCIe ports programming sequences to enable HSIOPC
HSIOPC/GPIO71 is used to control power to VCCHSIO, VCCUSB3PLL and VCCSATA3PLL in S0. PCH will drive HSIOPC low when all the high speed I/O controllers (xHCI, SATA, GbE and PCIe) are idle.
This patch added a few additional PCIe programming steps as required in 535127 BIOS Writer Guide Rev 2.3.0 to enable this power saving mode.
BUG=none BRANCH=none TEST=tested on Paine watching GPIO71 toggling as expected
Change-Id: Ica6954c125ec3129e2659168f1f23dc861ce5708 Signed-off-by: Stefan Reinauer reinauer@chromium.org Original-Commit-Id: e38f9ef57c480ca5ee420020eb80a1adb3c381d3 Original-Change-Id: I88ef125c681c8631e8b887f7ccf017b90b8c0f10 Original-Signed-off-by: Wenkai Du wenkai.du@intel.com Original-Reviewed-on: https://chromium-review.googlesource.com/238580 Original-Reviewed-by: Duncan Laurie dlaurie@chromium.org Reviewed-on: http://review.coreboot.org/9482 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi pgeorgi@google.com
See http://review.coreboot.org/9482 for details.
-gerrit