[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/adl: Update DCACHE_BSP_STACK_SIZE for Brox

[Julius Werner (Code Review)]

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik.

Julius Werner has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/83680?usp=email )

Change subject: soc/intel/adl: Update DCACHE_BSP_STACK_SIZE for Brox
......................................................................

Patch Set 2:

(2 comments)

Patchset:

PS2:
> I tried 64 KiB for Coreboot, but CAR is too full with that. Hence settled down to 32 KiB.

32 should be fine.

File src/soc/intel/alderlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/83680/comment/dde610c4_23462375?usp... :
PS2, Line 194: if BOARD_GOOGLE_BROX_COMMON
I think we should just update the value, not make it different for every board. The only reason not to increase it would be to maintain compatibility with older RO firmware but we already have branches for that.