[coreboot-gerrit] Change in ...coreboot[master]: mb/google/sarien: Disable PCH Gigabit LAN

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30096 )

Change subject: mb/google/sarien: Disable PCH Gigabit LAN
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mb/google/sarien: Disable PCH Gigabit LAN

There's no LAN connection on Arcada board, so disable PCH GBE.

BUG=N/A

Change-Id: I07c66df50dbe9fefd95a67b5af9e3f61ce6a18aa
Signed-off-by: Lijian Zhao 
Reviewed-on: https://review.coreboot.org/c/30096
Tested-by: build bot (Jenkins) 
Reviewed-by: Bora Guvendik 
---
M src/mainboard/google/sarien/variants/arcada/devicetree.cb
1 file changed, 1 insertion(+), 6 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Bora Guvendik: Looks good to me, approved

diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index fccec9f..924f51d 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -78,11 +78,6 @@
    	},
    }"

-	# PCIe port 9 for LAN
-	register "PcieRpEnable[8]" = "1"
-	register "PcieClkSrcUsage[0]" = "PCIE_CLK_LAN"
-	register "PcieClkSrcClkReq[0]" = "0"
-
    # PCIe port 10 for M.2 2230 WLAN
    register "PcieRpEnable[9]" = "1"
    register "PcieClkSrcUsage[2]" = "9"
@@ -250,6 +245,6 @@
    	device pci 1f.3 on  end # Intel HDA
    	device pci 1f.4 on  end # SMBus
    	device pci 1f.5 on  end # PCH SPI
-		device pci 1f.6 on  end # GbE
+		device pci 1f.6 off end # GbE
    end
 end