[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge: align AOAC code with Picasso

[Marshall Dawson (Code Review)]

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48181 )

Change subject: soc/amd/stoneyridge: align AOAC code with Picasso
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Patch Set 1: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/48181/1/src/soc/amd/stoneyridge/sou... 
File src/soc/amd/stoneyridge/southbridge.c:

https://review.coreboot.org/c/coreboot/+/48181/1/src/soc/amd/stoneyridge/sou... 
PS1, Line 154: FCH_AOAC_PWR_ON_DEV
Outside the scope of this patch but picasso clears both b0 and b1 in byte before ORing.  I can't recall whether that's because the PSP was leaving some stuff in non-default states.