Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45677 )
Change subject: soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function ......................................................................
soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function
Migrate ASL helper function like GRXS, GTXS, STXS, CTXS to ASL 2.0 syntax across CNL, ICL, JSL, SKL.
TEST=Able to build and boot Hatch, EVE and ICLRVP platform. Dump and disassemble DSDT to ensure GRXS,GTXS etc functions implementation remain unchanged prior and after this CL.
Change-Id: I0ebf1f86031eae25337d2dbeabb8893d9f19a14b Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45677 Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/cannonlake/acpi/gpio_op.asl M src/soc/intel/icelake/acpi/gpio.asl M src/soc/intel/skylake/acpi/gpio.asl 3 files changed, 20 insertions(+), 21 deletions(-)
Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/acpi/gpio_op.asl b/src/soc/intel/cannonlake/acpi/gpio_op.asl index 3c0ed66..7f2a40c 100644 --- a/src/soc/intel/cannonlake/acpi/gpio_op.asl +++ b/src/soc/intel/cannonlake/acpi/gpio_op.asl @@ -11,7 +11,7 @@ { VAL0, 32 } - And (GPIORXSTATE_MASK, ShiftRight (VAL0, GPIORXSTATE_SHIFT), Local0) + Local0 = GPIORXSTATE_MASK & (VAL0 >> GPIORXSTATE_SHIFT)
Return (Local0) } @@ -27,7 +27,7 @@ { VAL0, 32 } - And (GPIOTXSTATE_MASK, VAL0, Local0) + Local0 = GPIOTXSTATE_MASK & VAL0
Return (Local0) } @@ -43,7 +43,7 @@ { VAL0, 32 } - Or (GPIOTXSTATE_MASK, VAL0, VAL0) + VAL0 |= GPIOTXSTATE_MASK }
/* @@ -57,7 +57,7 @@ { VAL0, 32 } - And (Not (GPIOTXSTATE_MASK), VAL0, VAL0) + VAL0 &= ~GPIOTXSTATE_MASK }
/* @@ -76,10 +76,9 @@ { VAL0, 32 } - Store (VAL0, Local0) - And (Not (GPIOPADMODE_MASK), Local0, Local0) - And (ShiftLeft (Arg1, GPIOPADMODE_SHIFT, Arg1), GPIOPADMODE_MASK, Arg1) - Or (Local0, Arg1, VAL0) + Local0 = ~GPIOPADMODE_MASK & VAL0 + Arg1 = (Arg1 << GPIOPADMODE_SHIFT) & GPIOPADMODE_MASK + VAL0 = Local0 | Arg1 }
/* @@ -97,10 +96,10 @@ VAL0, 32 }
- If (LEqual (Arg1, 1)) { - And (Not (GPIOTXBUFDIS_MASK), VAL0, VAL0) - } ElseIf (LEqual (Arg1, 0)){ - Or (GPIOTXBUFDIS_MASK, VAL0, VAL0) + If (Arg1 == 1) { + VAL0 &= ~GPIOTXBUFDIS_MASK + } ElseIf (Arg1 == 0){ + VAL0 |= GPIOTXBUFDIS_MASK } }
@@ -119,9 +118,9 @@ VAL0, 32 }
- If (LEqual (Arg1, 1)) { - And (Not (GPIORXBUFDIS_MASK), VAL0, VAL0) - } ElseIf (LEqual (Arg1, 0)){ - Or (GPIORXBUFDIS_MASK, VAL0, VAL0) + If (Arg1 == 1) { + VAL0 &= ~GPIORXBUFDIS_MASK + } ElseIf (Arg1 == 0){ + VAL0 |= GPIORXBUFDIS_MASK } } diff --git a/src/soc/intel/icelake/acpi/gpio.asl b/src/soc/intel/icelake/acpi/gpio.asl index 43aa83c..f0a6fa0 100644 --- a/src/soc/intel/icelake/acpi/gpio.asl +++ b/src/soc/intel/icelake/acpi/gpio.asl @@ -114,7 +114,7 @@ { VAL0, 32 } - And (GPIORXSTATE_MASK, ShiftRight (VAL0, GPIORXSTATE_SHIFT), Local0) + Local0 = GPIORXSTATE_MASK & (VAL0 >> GPIORXSTATE_SHIFT)
Return (Local0) } diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl index 60e1cf5..de6ff42 100644 --- a/src/soc/intel/skylake/acpi/gpio.asl +++ b/src/soc/intel/skylake/acpi/gpio.asl @@ -119,7 +119,7 @@ { VAL0, 32 } - And (GPIORXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_RX_STATE_BIT), Local0) + Local0 = GPIORXSTATE_MASK & (VAL0 >> PAD_CFG0_RX_STATE_BIT)
Return (Local0) } @@ -135,7 +135,7 @@ { VAL0, 32 } - And (GPIOTXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_TX_STATE_BIT), Local0) + Local0 = GPIOTXSTATE_MASK & VAL0
Return (Local0) } @@ -151,7 +151,7 @@ { VAL0, 32 } - Or (GPIOTXSTATE_MASK, VAL0, VAL0) + VAL0 |= GPIOTXSTATE_MASK }
/* @@ -165,5 +165,5 @@ { VAL0, 32 } - And (Not (GPIOTXSTATE_MASK), VAL0, VAL0) + VAL0 &= ~GPIOTXSTATE_MASK }