[coreboot-gerrit] Change in coreboot[master]: soc/amd/cezanne: Move payload preload after ELOG init

[Raul Rangel (Code Review)]

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held.
Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59503 )

Change subject: soc/amd/cezanne: Move payload preload after ELOG init
......................................................................

soc/amd/cezanne: Move payload preload after ELOG init

We can only load so much while FSP-S is executing. If we don't finish
everything in time, the preloads will start competing with the ELOG init
that happens right after FSP-S. Since the payload isn't needed until the
end, we can move the preload call later in the boot flow.

This CL doesn't change any timings, instead it makes it so we can preload
the vga oprom while FSP-S loads.

BUG=b:179699789
TEST=Boot guybrush and verify timings didn't change.

Signed-off-by: Raul E Rangel 
Change-Id: Ib9baf43fab70f6a11d8a240e1dd94af70271c568
---
M src/soc/amd/cezanne/fsp_s_params.c
M src/soc/amd/cezanne/preload.c
2 files changed, 13 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/59503/1

diff --git a/src/soc/amd/cezanne/fsp_s_params.c b/src/soc/amd/cezanne/fsp_s_params.c
index 64cc722..64af58a 100644
--- a/src/soc/amd/cezanne/fsp_s_params.c
+++ b/src/soc/amd/cezanne/fsp_s_params.c
@@ -1,9 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

-#include <acpi/acpi.h>
 #include <device/pci.h>
 #include <fsp/api.h>
-#include <program_loading.h>
 #include <thread.h>

static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
@@ -23,15 +21,4 @@
    scfg->void_function = (uintptr_t)fsp_s_yield;

fsp_assign_vbios_upds(scfg);
-
-	/*
-	 * Since FSP-S takes a while to execute and performs no SPI operations, we can preload
-	 * while FSP-S executes.
-	 *
-	 * At this point FSP-S has been loaded into RAM. This means the cbfs_cache buffer used
-	 * for the FSP-S preload has been freed, so we don't have to worry about exhausting the
-	 * cbfs_cache.
-	 */
-	if (!acpi_is_wakeup_s3())
-		payload_preload();
 }
diff --git a/src/soc/amd/cezanne/preload.c b/src/soc/amd/cezanne/preload.c
index d8b0891..e713912 100644
--- a/src/soc/amd/cezanne/preload.c
+++ b/src/soc/amd/cezanne/preload.c
@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#include <acpi/acpi.h>
 #include <bootstate.h>
 #include <fsp/api.h>
+#include <program_loading.h>

static void start_fsps_preload(void *unused)
 {
@@ -9,3 +11,14 @@
 }

BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, start_fsps_preload, NULL);
+
+/*
+ * After FSP-S completes, we perform ELOG initialization. We don't want any preloads competing
+ * with ELOG init, so we trigger the additional preloads afterwards.
+ */
+static void start_post_elog_preloads(void *unused)
+{
+	if (!acpi_is_wakeup_s3())
+		payload_preload();
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, start_post_elog_preloads, NULL);