[coreboot-gerrit] Change in ...coreboot[master]: mb/lenovo/t430: Add support for MRC raminit

[Petr K (Code Review)]

Petr K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33539

Change subject: mb/lenovo/t430: Add support for MRC raminit
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mb/lenovo/t430: Add support for MRC raminit

Add support for MRC raminit and fill PEI data to make ports work.
Based on 32500

Signed-off-by: Petr K 
Change-Id: I3e097f7bb6b1de55b9e6a84efa4f9c630cee0745
---
M src/mainboard/lenovo/t430/Kconfig
M src/mainboard/lenovo/t430/devicetree.cb
M src/mainboard/lenovo/t430/romstage.c
3 files changed, 43 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/33539/1

diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig
index 7137b5e..7e52967 100644
--- a/src/mainboard/lenovo/t430/Kconfig
+++ b/src/mainboard/lenovo/t430/Kconfig
@@ -19,7 +19,6 @@
    select SERIRQ_CONTINUOUS_MODE
    select SOUTHBRIDGE_INTEL_C216
    select SYSTEM_TYPE_LAPTOP
-	select USE_NATIVE_RAMINIT
    select DRIVERS_LENOVO_HYBRID_GRAPHICS
    select MAINBOARD_HAS_LIBGFXINIT
    select GFX_GMA_INTERNAL_IS_LVDS
diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb
index 2731b69..a992377 100644
--- a/src/mainboard/lenovo/t430/devicetree.cb
+++ b/src/mainboard/lenovo/t430/devicetree.cb
@@ -30,6 +30,32 @@
    	end
    end

+    # PEI data
+	
+	register "spd_addresses" = "{ 0xa0, 0x00, 0xa2, 0x00 }"
+	register "ts_addresses" = "{ 0x00, 0x00, 0x00, 0x00 }"
+		
+	register "max_mem_clock_mhz" = "800" # DDR3-1600
+	
+		register "usb_port_config" = "{
+	
+            { 1, 1, 0x0040 },
+            { 1, 1, 0x0040 },
+            { 1, 2, 0x0040 },
+            { 1, 1, 0x0040 },
+            { 1, 1, 0x0040 },
+            { 1, 0, 0x0040 },
+            { 0, 0, 0x0040 },
+            { 1, 2, 0x0040 },
+            { 1, 0, 0x0040 },
+            { 1, 1, 0x0040 },
+            { 1, 0, 0x0040 },
+            { 1, 0, 0x0040 },
+            { 1, 3, 0x0040 },
+            { 1, 1, 0x0040 },
+	        
+	        }"
+	
    device domain 0x0 on
    	chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
    		register "c2_latency" = "0x0065"
diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c
index db50bb3..fa46dc3 100644
--- a/src/mainboard/lenovo/t430/romstage.c
+++ b/src/mainboard/lenovo/t430/romstage.c
@@ -20,6 +20,7 @@
 #include <ec/lenovo/pmh7/pmh7.h>
 #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit.h>
 #include <device/device.h>
 #include <device/pci.h>

@@ -96,3 +97,19 @@
    read_spd(&spd[0], 0x50, id_only);
    read_spd(&spd[2], 0x51, id_only);
 }
+
+	
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+	
+{
+	
+}
+	
+	
+int mainboard_should_reset_usb(int s3resume)
+	
+{
+	
+	return !s3resume;
+	
+}