[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add SoC API to make use SMM common code

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22870

Change subject: soc/intel/cannonlake: Add SoC API to make use SMM common code
......................................................................

soc/intel/cannonlake: Add SoC API to make use SMM common code

Add SoC API to detect any illegal access to write into the
BIOS located in the FWH.

Change-Id: If526cbae9afee47fa272bdf74e04416aff100e88
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/cpu.c
M src/soc/intel/cannonlake/pmc.c
M src/soc/intel/cannonlake/smihandler.c
3 files changed, 32 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/22870/1

diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index 2dffccb..728ab9c 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -26,6 +26,7 @@
 #include <soc/cpu.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
+#include <soc/pm.h>
 #include <soc/smm.h>

static void soc_fsp_load(void)
@@ -216,7 +217,7 @@
     * Now that all APs have been relocated as well as the BSP let SMIs
     * start flowing.
     */
-	smm_southbridge_enable();
+	smm_southbridge_enable(PWRBTN_EN | GBL_EN);

/* Lock down the SMRAM space. */
    smm_lock();
diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c
index a6ad0ad..92f45a8 100644
--- a/src/soc/intel/cannonlake/pmc.c
+++ b/src/soc/intel/cannonlake/pmc.c
@@ -51,7 +51,7 @@
  * Set PMC register to know which state system should be after
  * power reapplied
  */
-void pmc_soc_restore_power_failiure(void)
+void pmc_soc_restore_power_failure(void)
 {
    pmc_set_afterg3(CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL);
 }
diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c
index 0653e9f..6c5e923 100644
--- a/src/soc/intel/cannonlake/smihandler.c
+++ b/src/soc/intel/cannonlake/smihandler.c
@@ -15,6 +15,8 @@
  * GNU General Public License for more details.
  */

+#include <console/console.h>
+#include <intelblocks/fast_spi.h>
 #include <intelblocks/smihandler.h>
 #include <soc/pm.h>

@@ -23,6 +25,33 @@
    return &em64t101_smm_ops;
 }

+void smihandler_check_illegal_access(uint32_t tco_sts)
+{
+	if (tco_sts & (1 << 8)) { /* BIOSWR */
+		if (IS_ENABLED(CONFIG_SPI_FLASH_SMM)) {
+			if (fast_spi_wpd_status()) {
+				/*
+				 * BWE is RW, so the SMI was caused by a
+				 * write to BWE, not by a write to the BIOS
+				 *
+				 * This is the place where we notice someone
+				 * is trying to tinker with the BIOS. We are
+				 * trying to be nice and just ignore it. A more
+				 * resolute answer would be to power down the
+				 * box.
+				 */
+				printk(BIOS_DEBUG, "Switching back to RO\n");
+				fast_spi_enable_wp();
+			} /* No else for now? */
+		}
+	}
+}
+
+/* SMI handlers that should be serviced in SCI mode too. */
+uint32_t smi_handler_sci_mask =
+	SMI_HANDLER_SCI_EN(APM_STS_BIT) |
+	SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT);
+
 const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
    [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
    [APM_STS_BIT] = smihandler_southbridge_apmc,