Attention is currently required from: Arthur Heymans, Subrata Banik, Christian Walter, Tim Wawrzynczak, Andrey Petrov. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63007 )
Change subject: drivers/intel/fsp2_0: Add native implementation for FSP Debug Handler ......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Patchset:
PS2:
Fun fact: the USF spec thinks this a bad idea: https://universalscalablefirmware.github.io/documentation/6_debug.html#trace.... It says the Soc Abstraction Layer (basically FSP) should be in charge of selecting where console gets outputted.
I guess the term BIOS being used their is misleading, because the definition on BIOS is now evolved over time and unless specified some thing like silicon ref aka FSP or platform code aka coreboot, this is not clear when someone says "BIOS shall support sending trace messages to all BIOS accessible HW interfaces on the platform.'
I can replace BIOS with coreboot here for my easy understanding and say "yes, coreboot would like to support sending traces to coreboot accessible HW interface for the platform."
Ok that would make sense, however "BIOS modules don’t control which trace output is used. SAL layer shall implement a middleware trace class which routes the messages to enabled interfaces such as NPK or UART." seems to indicate otherwise? Anyway no point in discussing things when terminology isn't clear to either of us.