Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55253 )
Change subject: soc/intel/alderlake: Add inline comment to cse_fw_sync() ......................................................................
soc/intel/alderlake: Add inline comment to cse_fw_sync()
The patch adds comment for cse_fw_sync()
TEST= Build Brya coreboot
Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Change-Id: I0a5745b63831b2c3f7bfbb44a650bdeb48f589ab --- M src/soc/intel/alderlake/romstage/romstage.c 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/55253/1
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index d7ef14d..e6a9592 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -134,6 +134,9 @@ * cse_fw_sync() must be called after DRAM initialization as * HMRFPO_ENABLE HECI command (which is used by cse_fw_sync()) * is expected to be executed after DRAM initialization. + * When AP starts from G3, cse_fw_sync() triggers GLOBAL RESET after + * marking CSE's next boot partition to RW. Also, it trigger CSE Firmware update + * if CSE RW blob's version is different from CSE RW version. */ if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) cse_fw_sync();