Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao.
Hello Zheng Bao,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/85647?usp=email
to review the following change.
Change subject: soc/amd: Add A/B recovery support to AMD SOC ......................................................................
soc/amd: Add A/B recovery support to AMD SOC
1. Add A/B data address to command line. 2. Enable CBFS verificatin if A/B recovery is enabled. 3. Setup a backup region B and copy duplicated CBFS modules.
Change-Id: Iaa8c4175285c5ceb16972ea57f0c0ca0403d8b84 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.mk M src/soc/amd/common/Makefile.mk M src/soc/amd/common/block/psp/Makefile.mk 4 files changed, 57 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/85647/1
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index c6846a1..cd1cd07 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -410,7 +410,7 @@
config PSP_AB_RECOVERY bool "Use A/B Recovery scheme" - default n + default y help Enable the PSP A/B Recovery mechanism
diff --git a/src/soc/amd/cezanne/Makefile.mk b/src/soc/amd/cezanne/Makefile.mk index 3983aaa..7cc0cd9 100644 --- a/src/soc/amd/cezanne/Makefile.mk +++ b/src/soc/amd/cezanne/Makefile.mk @@ -48,6 +48,14 @@
CEZANNE_FW_B_POSITION=$(call int-add, \ $(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) + +ifeq ($(CONFIG_PSP_AB_RECOVERY), y) +CEZANNE_FW_A_RECOVERY=$(call int-add, \ + $(call get_fmap_value,FMAP_SECTION_PARTITIION_START) 4096) +CEZANNE_FW_B_RECOVERY=$(call int-add, \ + $(call get_fmap_value,FMAP_SECTION_BCOPY_START) 4096) +endif + # # PSP Directory Table items # @@ -182,10 +190,12 @@ OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table)
-OPT_RECOVERY_AB=$(call add_opt_prefix, $(CONFIG_PSP_RECOVERY_AB), --recovery-ab) +OPT_RECOVERY_AB=$(if $(CONFIG_PSP_AB_RECOVERY), --recovery-ab) OPT_BIOS_AMDCOMPRESS=$(if $(CONFIG_CBFS_VERIFICATION), --elfcopy, --compress) OPT_BIOS_FWCOMPRESS=$(if $(CONFIG_CBFS_VERIFICATION), --bios-bin-uncomp)
+OPT_RECOVERY_AB+=$(if $(CONFIG_PSP_AB_RECOVERY), --recovery-a-location $(call _tohex, $(CEZANNE_FW_A_RECOVERY)) --recovery-b-location $(call _tohex, $(CEZANNE_FW_B_RECOVERY))) + AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ $(OPT_PSP_NVRAM_BASE) \ $(OPT_PSP_NVRAM_SIZE) \ diff --git a/src/soc/amd/common/Makefile.mk b/src/soc/amd/common/Makefile.mk index 626260f..dcdeb71 100644 --- a/src/soc/amd/common/Makefile.mk +++ b/src/soc/amd/common/Makefile.mk @@ -40,22 +40,49 @@
amd_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/*U?odePatch*.bin)
+AB_RECOVERY=$(CONFIG_PSP_AB_RECOVERY) +ifeq ($(AB_RECOVERY),y) +BOOTBLOCK_SOURCE=$(obj)/amdfw.rom.ra +BOOTBLOCK_SOURCE_B=$(obj)/amdfw.rom.rb +else +BOOTBLOCK_SOURCE=$(obj)/amdfw.rom +endif + ifeq ($(CONFIG_RESET_VECTOR_IN_RAM),y) -$(objcbfs)/bootblock.bin: $(obj)/amdfw.rom $(obj)/fmap_config.h +$(objcbfs)/bootblock.bin: $(BOOTBLOCK_SOURCE) $(obj)/fmap_config.h cp $< $@
amdfw_region_start=$(subst $(spc),,FMAP_SECTION_$(call regions-for-file,apu/amdfw)_START) +ifeq ($(AB_RECOVERY),y) +amdfw_offset=4096 +$(call add_intermediate, add_amdfw, $(obj)/amdfw.rom) + printf " DD Adding AMD Firmware at ROM offset 0x%x\n" \ + "$(CONFIG_AMD_FWM_POSITION)" + $(CBFSTOOL) $(obj)/coreboot.pre write -r EFS -f $(obj)/amdfw.rom --fill-upward + +$(obj)/amdfw.rom.rb: $(obj)/amdfw.rom +$(obj)/amdfw.rom.ra: $(obj)/amdfw.rom + +else amdfw_offset=$(call int-subtract, \ $(CONFIG_AMD_FWM_POSITION) \ $(call int-subtract, \ $(call get_fmap_value,$(amdfw_region_start)) \ $(call get_fmap_value,FMAP_SECTION_FLASH_START))) +endif
-add_bootblock = \ - $(CBFSTOOL) $(1) add -f $(2) -n apu/amdfw -t amdfw \ - -b $(amdfw_offset) -r $(call regions-for-file,apu/amdfw) \ - $(CBFSTOOL_ADD_CMD_OPTIONS) - +add_bootblock= \ + for region in $(subst $(comma),$(spc),$(call regions-for-file,apu/amdfw)); do \ + if [ $$region = COREBOOT ]; then \ + $(CBFSTOOL) $(1) add -f $(2) -n apu/amdfw -t amdfw \ + -b $(amdfw_offset) -r $$region \ + $(CBFSTOOL_ADD_CMD_OPTIONS) ; \ + elif [ $$region = COREBOOTB ]; then \ + $(CBFSTOOL) $(1) add -f $(obj)/amdfw.rom.rb -n apu/amdfw -t amdfw \ + -b $(amdfw_offset) -r $$region \ + $(CBFSTOOL_ADD_CMD_OPTIONS) ; \ + fi ; \ + done endif # ifeq ($(CONFIG_RESET_VECTOR_IN_RAM),y)
ifeq ($(CONFIG_VBOOT_GSCVD),y) diff --git a/src/soc/amd/common/block/psp/Makefile.mk b/src/soc/amd/common/block/psp/Makefile.mk index dc811f90..0761cba 100644 --- a/src/soc/amd/common/block/psp/Makefile.mk +++ b/src/soc/amd/common/block/psp/Makefile.mk @@ -38,3 +38,15 @@ ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_SPL) += spl_fuse.c
endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2 + +regions-for-file += $(if $(filter \ + %/romstage \ + %/ramstage \ + %/dsdt.aml \ + %/payload \ + fspm%.bin \ + fsps%.bin \ + cpu_microcode%.bin \ + pci%.rom \ + apu/amdfw \ + ,$(1)), $(if $(call get_fmap_value,FMAP_SECTION_BCOPY_START),COREBOOTB))