John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43980 )
Change subject: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43980/2/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/43980/2/src/soc/intel/tigerlake/fsp... PS2, Line 120: (cpu_id == CPUID_TIGERLAKE_A0)
Maybe encapsulate this in a function `static bool can_enable_tcss_d3cold(void)`? This would result i […]
Not sure whether we need to create a function for this one line of code. Others put comments to consider configuring D3Cold only through devicetree/override. Let us wait for the decision.
https://review.coreboot.org/c/coreboot/+/43980/3/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/43980/3/src/soc/intel/tigerlake/fsp... PS3, Line 123: TcssD3ColdEnable
if the expected setting is for D3ColdEnable to be enabled, […]
D3ColdEnable setting is expected to be enabled. There is only D3ColdEnable in fsp upd and no D3ColdDisable. So it appears no need to consider adding TcssD3ColdDisable into soc_intel_tigerlake_config structure. This patch would disable D3Cold for pre-QS and enable D3Cold for QS if platform's TcssD3ColdEnable is set "1", which is expected.