[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Configure FSP UPDs for minimum assertion widths

[Furquan Shaikh (Code Review)]

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Rizwan Qureshi, Nick Vaccaro, Sridhar Siricilla, Meera Ravindranath, Patrick Rudolph, Karthik Ramasubramanian.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51846 )

Change subject: soc/intel/alderlake: Configure FSP UPDs for minimum assertion widths
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Patch Set 2:

(1 comment)

File src/soc/intel/alderlake/chip.h:

https://review.coreboot.org/c/coreboot/+/51846/comment/a568b770_29097147 
PS2, Line 316: 	/*
             : 	 * SLP_S3 Minimum Assertion Width Policy
             : 	 *  1 = 60us
             : 	 *  2 = 1ms
             : 	 *  3 = 50ms (default)
             : 	 *  4 = 2s
             : 	 */
             : 	uint8_t PchPmSlpS3MinAssert;
             : 
             : 	/*
             : 	 * SLP_S4 Minimum Assertion Width Policy
             : 	 *  1 = 1s (default)
             : 	 *  2 = 2s
             : 	 *  3 = 3s
             : 	 *  4 = 4s
             : 	 */
             : 	uint8_t PchPmSlpS4MinAssert;
             : 
             : 	/*
             : 	 * SLP_SUS Minimum Assertion Width Policy
             : 	 *  1 = 0ms
             : 	 *  2 = 500ms
             : 	 *  3 = 1s
             : 	 *  4 = 4s (default)
             : 	 */
             : 	uint8_t PchPmSlpSusMinAssert;
             : 
             : 	/*
             : 	 * SLP_A Minimum Assertion Width Policy
             : 	 *  1 = 0ms
             : 	 *  2 = 4s
             : 	 *  3 = 98ms
             : 	 *  4 = 2s (default)
             : 	 */
             : 	uint8_t PchPmSlpAMinAssert;
             : 
             : 	/*
             : 	 * PCH PM Reset Power Cycle Duration
             : 	 *  0 = 4s (default)
             : 	 *  1 = 1s
             : 	 *  2 = 2s
             : 	 *  3 = 3s
             : 	 *  4 = 4s
             : 	 *
             : 	 * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the
             : 	 * stretch duration programmed in the following registers:
             : 	 *  - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
             : 	 *  - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
             : 	 *  - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
             : 	 *  - PM_CFG.SLP_LAN_MIN_ASST_WDTH
             : 	 */
             : 	uint8_t PchPmPwrCycDur;
> Other option would be to just use the enums as symbolic only, and leave their values specified as th […]

Conversion might be required one way or the other. This configuration has to be performed in coreboot before FSP runs because coreboot could trigger a global reset for reasons like CSE RO->RW jump. So, we need to use the same configuration in coreboot as well as to pass into FSP UPD (I think we should ask Intel to add a UPD option indicating do not change min assert values). But, until then, we can use the enum as you suggested and configure the register in coreboot and convert that into appropriate UPDs for FSP.